The patch is modified based on the review comments from Richard, Bernd and
David.
The following changes are done to incorporate the comments received on the
previous mail.
1. With this patch the liveness of the Loop is not stored on the LOOPDATA
structures. The liveness is calculated based on
Hi,
even the latest versions of Windows still guarantee only a 4-byte alignment of
the stack in 32-bit mode, which doesn't play nice with some SSE instructions.
That's why some projects enable -mstackrealign by default on 32-bit Windows:
https://bugzilla.mozilla.org/show_bug.cgi?id=631252
This
On Mon, Dec 14, 2015 at 08:17:33PM +0300, Ilya Verbin wrote:
> Here is an updated patch. Now MSB is set in both tables, and
> gomp_unload_image_from_device is changed. I've verified using simple DSO
> testcase, that memory on target is freed after dlclose.
> bootstrap and make check on x86_64-lin
tbsaunde+...@tbsaunde.org writes:
> diff --git a/gcc/config.gcc b/gcc/config.gcc
> index 882e413..59f77da 100644
> --- a/gcc/config.gcc
> +++ b/gcc/config.gcc
> @@ -237,7 +237,7 @@ md_file=
> # Obsolete configurations.
> case ${target} in
> # Currently there are no obsolete targets.
> - nothing
Hi,
the attached patch simplifies vector conditional statements like
v < 0 ? -1 : 0 into v >> 31. The code is largely based on the x86
implementation of this feature by Jakub Jelinek. In future, (and if
useful for more backends) it could make sense to implement this directly
at tree-level.
Bootst
ping
This patch series generalizes CCMP by adding FCCMP support and enabling more
optimizations.
The first patch simplifies the representation of CCMP patterns by using
if-then-else which closely
matches real instruction semantics. As a result the existing special CC modes
and functions are n
ping
> -Original Message-
> From: Wilco Dijkstra [mailto:wilco.dijks...@arm.com]
> Sent: 17 November 2015 18:36
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH 2/4 v2][AArch64] Add support for FCCMP
>
> (v2 version removes 4 enums)
>
> This patch adds support for FCCMP. This is trivial w
ping
> -Original Message-
> From: Wilco Dijkstra [mailto:wilco.dijks...@arm.com]
> Sent: 13 November 2015 16:03
> To: 'gcc-patches@gcc.gnu.org'
> Subject: [PATCH 3/4][AArch64] Add CCMP to rtx costs
>
> This patch adds support for rtx costing of CCMP. The cost is the same as
> int/FP comp
ping
> -Original Message-
> From: Wilco Dijkstra [mailto:wilco.dijks...@arm.com]
> Sent: 13 November 2015 16:03
> To: 'gcc-patches@gcc.gnu.org'
> Subject: [PATCH 4/4][AArch64] Cost CCMP instruction sequences to choose
> better expand order
>
> This patch adds CCMP selection based on rtx
ping
> -Original Message-
> From: Wilco Dijkstra [mailto:wilco.dijks...@arm.com]
> Sent: 06 November 2015 20:06
> To: 'gcc-patches@gcc.gnu.org'
> Subject: [PATCH][AArch64] Add TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
>
> This patch adds support for the TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
ping
> -Original Message-
> From: Wilco Dijkstra [mailto:wilco.dijks...@arm.com]
> Sent: 19 November 2015 18:12
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH][ARM] Enable fusion of AES instructions
>
> Enable instruction fusion of AES instructions on ARM for Cortex-A53 and
> Cortex-A57
Kyrill Tkachov wrote:
> On 14/10/15 13:30, Wilco Dijkstra wrote:
> > Enable instruction fusion of dependent AESE; AESMC and AESD; AESIMC pairs.
> > This can give up to 2x
> > speedup on many AArch64 implementations. Also model the crypto instructions
> > on Cortex-A57 according
> > to the Optimiz
ping
> -Original Message-
> From: Wilco Dijkstra [mailto:wdijk...@arm.com]
> Sent: 28 October 2015 17:33
> To: GCC Patches
> Subject: [PATCH][AArch64] Avoid emitting zero immediate as zero register
>
> Several instructions accidentally emit wzr/xzr even when the pattern
> specifies an im
Add support for vector permute cost since various permutes can expand into a
complex
sequence of instructions. This fixes major performance regressions due to
recent changes
in the SLP vectorizer (which now vectorizes more aggressively and emits many
complex
permutes).
Set the cost to > 1 fo
On Tue, Dec 15, 2015 at 10:32:08AM +, Wilco Dijkstra wrote:
> ping
>
> This patch series generalizes CCMP by adding FCCMP support and enabling more
> optimizations.
> The first patch simplifies the representation of CCMP patterns by using
> if-then-else which closely
> matches real instruc
On 12/11/2015 08:14 PM, Daniel Kahn Gillmor wrote:
I think you mean so that we would just ignore -fdebug-prefix-map
entirely when writing DW_AT_producer, so that you could build
reproducibly with (for example):
gcc -fdebug-prefix-map=$(pwd)=/usr/src
We'd considered and discarded this approach
Dear all,
I've added myself to Write After Approval maintainers.
Committed revision 231647.
Index: MAINTAINERS
===
--- MAINTAINERS(revision 231646)
+++ MAINTAINERS(working copy)
@@ -388,6 +388,7 @@
Ansgar Esztermann
On Tue, Dec 15, 2015 at 02:07:40PM +0100, Alessandro Fanfarillo wrote:
> I've added myself to Write After Approval maintainers.
> --- ChangeLog(revision 231646)
> +++ ChangeLog(working copy)
> @@ -1,3 +1,7 @@
> +2015-12-15 Alessandro Fanfarillo
Two spaces before < instead of one.
On 12/14/2015 02:05 PM, Andreas Krebbel wrote:
the constraint modifier % applies to all the alternatives of a pattern
and hence is mostly added to the first constraint of an operand. IRA
currently ignores it if the alternative with the % gets disabled by
using the `enabled' attribute or if it is
On 12/14/2015 01:25 PM, Kyrill Tkachov wrote:
For this PR I want to teach combine to deal with unrecognisable patterns
that contain a sub-expression like
(x + x) by transforming it into (x << 1) and trying to match the result.
This is because some instruction
sets like arm and aarch64 can combine
Committed as revision 231649 on trunk and as revision 231650 on gcc-5-branch.
Thanks.
2015-12-14 20:02 GMT+01:00 Tobias Burnus :
> Dear Alessandro,
>
> Alessandro Fanfarillo wrote:
>>
>> the compiler returns an ICE when a coarray critical section is used
>> inside a module procedure.
>> The symbo
This patch removes unnecessary mode promotions in argument and return
handling. We also move the handling of thee return mode directly into
nvptx_function value, rather than have that return the mode and then detect
emission of the move that uses it.
nathan
2015-12-15 Nathan Sidwell
Mike Stump writes:
> On Dec 14, 2015, at 2:40 AM, Rainer Orth
> wrote:
>> As described in PR PR target/67973, newer assemblers on Mac OS X, which
>> are based on LLVM instead of gas, don't support .stab* directives any
>> longer. The following patch detects this situation and tries to fall
>>
On Tue 2015-12-15 07:19:30 -0500, Bernd Schmidt wrote:
> On 12/11/2015 08:14 PM, Daniel Kahn Gillmor wrote:
>> Here's a one-liner patch for this approach (also at
>> https://gcc.gnu.org/bugzilla/attachment.cgi?id=37007):
>
> I think that one-liner is fine, even for now.
great! what would be the n
On 12/14/2015 01:25 PM, Kyrill Tkachov wrote:
PR 68651 is a code quality regression for GCC 5 and GCC 6 that was
introduced due to updated rtx costs
for -mcpu=cortex-a53 that affected expansion. The costs changes were
correct (to the extent that rtx
costs have any meaning) and I think this is a
On 15/12/15 14:22, Bernd Schmidt wrote:
> On 12/14/2015 01:25 PM, Kyrill Tkachov wrote:
>> PR 68651 is a code quality regression for GCC 5 and GCC 6 that was
>> introduced due to updated rtx costs
>> for -mcpu=cortex-a53 that affected expansion. The costs changes were
>> correct (to the extent tha
On 12/15/2015 03:33 PM, Richard Earnshaw wrote:
It's also possible that this would explicitly break some other
optimization passes (such as the way in which multiplies are synthesised
with shift/add operations).
How so? IMO such a change would make cost calculations more accurate and
should h
On Fri, Dec 11, 2015 at 7:27 AM, Martin Jambor wrote:
> Hi,
>
> PR 66616 happens because in find_more_scalar_values_for_callers_subset
> we do not do the same thunk checks like we do in
> propagate_constants_accross_call. I am in the process of
> bootstrapping and testing the following patch to f
Here, missing TREE_NO_WARNING on an artificial variable caused bogus
-Wunused-value warning.
Bootstrapped/regtested on x86_64-linux, ok for trunk?
2015-12-15 Marek Polacek
PR c/68907
* c-typeck.c (build_atomic_assign): Set TREE_NO_WARNING on an
artificial decl.
On 12/15/2015 03:59 PM, Marek Polacek wrote:
Here, missing TREE_NO_WARNING on an artificial variable caused bogus
-Wunused-value warning.
Bootstrapped/regtested on x86_64-linux, ok for trunk?
2015-12-15 Marek Polacek
PR c/68907
* c-typeck.c (build_atomic_assign): Set TREE_NO
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Steve Ellcey
> Sent: Wednesday, December 09, 2015 1:34 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Moore, Catherine; matthew.fort...@imgtec.com
> Subject: [Patch] Fix for MIPS PR t
On 10/12/15 10:45, Ramana Radhakrishnan wrote:
On Tue, Dec 8, 2015 at 7:45 AM, Christian Bruel wrote:
Hi Matthew,
On 26/11/15 16:01, Matthew Wahab wrote:
Hello,
This patch adds the feature macro __ARM_FEATURE_QRDMX to indicate the
presence of the ARMv8.1 instructions vqrdmlah and vqrdmlsh.
On 10/12/15 10:49, Ramana Radhakrishnan wrote:
On Mon, Dec 7, 2015 at 4:10 PM, Matthew Wahab
wrote:
On 27/11/15 17:11, Matthew Wahab wrote:
On 27/11/15 13:44, Christophe Lyon wrote:
On 26/11/15 16:02, Matthew Wahab wrote
This patch adds ARMv8.1 support to GCC Dejagnu, to allow ARM tests t
On 12/15/2015 03:14 PM, Daniel Kahn Gillmor wrote:
On Tue 2015-12-15 07:19:30 -0500, Bernd Schmidt wrote:
On 12/11/2015 08:14 PM, Daniel Kahn Gillmor wrote:
Here's a one-liner patch for this approach (also at
https://gcc.gnu.org/bugzilla/attachment.cgi?id=37007):
I think that one-liner is fin
Sorry about that.
Committed revision 231657
Index: ChangeLog
===
--- ChangeLog(revision 231656)
+++ ChangeLog(working copy)
@@ -1,4 +1,4 @@
-2015-12-15 Alessandro Fanfarillo
+2015-12-15 Alessandro Fanfarillo
* MAIN
On 12/15/2015 04:09 PM, Christian Bruel wrote:
in "normal" mode, the TYPE_MODE for vector_type __simd64_int8_t is set
to V8QImode by arm_vector_mode_supported_p during the builtins type
initializations, thanks to TARGET_NEON set bu the global flag.
Now, in LTO mode the streamer writes the inform
Hi Bernd,
On 15/12/15 14:22, Bernd Schmidt wrote:
On 12/14/2015 01:25 PM, Kyrill Tkachov wrote:
PR 68651 is a code quality regression for GCC 5 and GCC 6 that was
introduced due to updated rtx costs
for -mcpu=cortex-a53 that affected expansion. The costs changes were
correct (to the extent tha
On 12/14/2015 07:49 PM, Trevor Saunders wrote:
+ hash_map (const hash_map &h, bool ggc = false,
+ bool gather_mem_stats = true CXX_MEM_STAT_INFO)
sorry about the late response, but wouldn't it be better to make this
and the hash_table constructor explicit? Its probably less importa
When issuing diagnostics for _Static_assert, we currently ignore the
location/range of the asserted expression, and instead use the
location/range of the first token within it, which can be
incorrect for compound expressions:
error: expression in static assertion is not constant
_Static_assert
We can use rich_location and the new diagnostic_show_locus to print
*both* locations when complaining about a bogus string concatenation
in the C++ FE, giving e.g.:
test.C:3:24: error: unsupported non-standard concatenation of string literals
const void *s = u8"a" u"b";
~ ^
On Tue 2015-12-15 11:08:23 -0500, Bernd Schmidt wrote:
> I'm guessing you don't have an account
I don't have an account (though i'd be happy to set one up if you point
me toward the process).
> so I'll bootstrap and test it and then commit.
fwiw, I've tested it myself, and can confirm that it do
Hi Richard,
I re-designed the patch to determine ability of loop masking on fly of
vectorization analysis and invoke it after loop transformation.
Test-case is also provided.
what is your opinion?
Thanks.
Yuri.
ChangeLog::
2015-12-15 Yuri Rumyantsev
* config/i386/i386.c (ix86_builtin_vector
Hi!
On Wed, 9 Dec 2015 17:56:13 +0800, "Thomas Preud'homme"
wrote:
> c-c++-common/attr-simd-3.c fails to compile on arm-none-eabi targets due to
> -fcilkplus needing -pthread which is not available for those targets. This
> patch solves this issue by adding a condition to the cilkplus effectiv
On Tue, Dec 15, 2015 at 10:32:50AM +, Wilco Dijkstra wrote:
> ping
>
> > -Original Message-
> > From: Wilco Dijkstra [mailto:wilco.dijks...@arm.com]
> > Sent: 17 November 2015 18:36
> > To: gcc-patches@gcc.gnu.org
> > Subject: [PATCH 2/4 v2][AArch64] Add support for FCCMP
> >
> > (v2
On Tue, Dec 15, 2015 at 10:33:22AM +, Wilco Dijkstra wrote:
> ping
>
> > -Original Message-
> > From: Wilco Dijkstra [mailto:wilco.dijks...@arm.com]
> > Sent: 13 November 2015 16:03
> > To: 'gcc-patches@gcc.gnu.org'
> > Subject: [PATCH 3/4][AArch64] Add CCMP to rtx costs
> >
> > This
Hi all,
As part of the war on conditional compilation here's an #if check on
WORD_REGISTER_OPERATIONS that
seems to have been missed out.
Bootstrapped and tested on arm, aarch64, x86_64.
Is it still ok to commit these kinds of conditional compilation conversions?
Thanks,
Kyrill
2015-12-15 K
The first patch fixes an inconsistency between the return type and the
function body, as described in the PR.
The second patch removes the TR1 return type support from _Mu, because
it isn't necessary in C++11. The third patch is because the second one
accidentally removed a "volatile" (removing t
Hi all,
This converts the preprocessor check for WORD_REGISTER_OPERATIONS into a
runtime one
in rtlanal.c.
Since this one was in combination with an "#if defined" and used to guard an
if-statement
I'd appreciate it if someone gave it a double-check that I dind't screw up the
intended
behaviou
Adding Bernd - would you mind reviewing the ccmp.c change please?
> -Original Message-
> From: James Greenhalgh [mailto:james.greenha...@arm.com]
> Sent: 15 December 2015 16:42
> To: Wilco Dijkstra
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH 2/4 v2][AArch64] Add support for FCCMP
>
Hi all,
This converts the preprocessor checks for WORD_REGISTER_OPERATIONS into runtime
checks
in reload.c.
Since this one is used to guard part of a large condition, I'd appreciate it if
someone
double-checks that the logic is still equivalent.
Bootstrapped and tested on arm, aarch64, x86_64
Hi all,
This converts the preprocessor check for WORD_REGISTER_OPERATIONS into a
runtime check
in reload1.c.
Since this one is used to guard part of a condition, I'd appreciate it if
someone
double-checks that the logic is still equivalent.
Bootstrapped and tested on arm, aarch64, x86_64.
Ok
On Dec 15, 2015, at 5:35 AM, Rainer Orth wrote:
> Right: I'm effectively keeping just the first configure test for .stabs
> support in the assembler to enable or disable
> DBX_DEBUG/DBX_DEBUGGING_INFO. I'll post it later since …
> ... testing revealed another instance of static assumptions which
On 12/14/2015 01:07 PM, Jan-Benedict Glaw wrote:
On Mon, 2015-12-14 18:54:28 +, Moore, Catherine
wrote:
avr-rtems
http://toolchain.lug-owl.de/buildbot/show_build_details.php?id=478544
mipsel-elf
http://toolchain.lug-owl.de/buildbot/show_build_details.php?id=478
On 15/12/15 10:33, Wilco Dijkstra wrote:
-Original Message-
From: Wilco Dijkstra [mailto:wilco.dijks...@arm.com]
Sent: 13 November 2015 16:03
To: 'gcc-patches@gcc.gnu.org'
Subject: [PATCH 4/4][AArch64] Cost CCMP instruction sequences to choose better
expand order
This patch adds CCMP se
On 12/10/15 06:34, Jakub Jelinek wrote:
I'm aware of some duplication in expand_omp_for_* functions, and some of the
obvious duplications were already moved to helper functions. But in these
cases the number of differences is even significantly bigger too, so having
just one function that would
This fixes a missing argument to the futex syscall.
Tested powerpc64le-linux. This needs to be fixed for gcc-5 and trunk.
commit ea5726fb770a1e89f6102c903f828ec6d71a1e3d
Author: Jonathan Wakely
Date: Tue Dec 15 18:34:52 2015 +
libstdc++/68921 add timeout argument to futex(2)
On Dec 11, 2015, at 6:09 AM, Jeff Law wrote:
> On 12/11/2015 02:22 AM, Eric Botcazou wrote:
>>> This patch allows a target to increase the cost of anti-deps to better
>>> reflect the actual cost on the machine.
>>
>> But it can already do it via the TARGET_SCHED_ADJUST_COST hook, can't it?
> And
On Dec 11, 2015, at 1:22 AM, Eric Botcazou wrote:
>> This patch allows a target to increase the cost of anti-deps to better
>> reflect the actual cost on the machine.
>
> But it can already do it via the TARGET_SCHED_ADJUST_COST hook, can't it?
The undocumented TARGET_SCHED_ADJUST_COST_2 seems a
On Wed, 2015-12-09 at 18:44 +0100, Bernd Schmidt wrote:
> On 12/09/2015 05:58 PM, David Malcolm wrote:
> > On Wed, 2015-11-04 at 14:56 +0100, Bernd Schmidt wrote:
> >>
> >> This seems like fairly low impact but also low cost, so I'm fine with it
> >> in principle. I wonder whether the length of the
"Ulrich Weigand" writes:
> Dominik Vogt wrote:
>
>> +; Note: Although CONST_INT and CONST_DOUBLE are not handled in this
>> predicate,
>> +; at least one of them needs to appear or otherwise safe_predicate_mode will
>> +; assume that a DImode LABEL_REF is not accepted either (see genrecog.c).
>
>
On Tue, 2015-12-15 at 18:46 +, Jonathan Wakely wrote:
> This fixes a missing argument to the futex syscall.
>
> Tested powerpc64le-linux. This needs to be fixed for gcc-5 and trunk.
>
OK. Thanks!
this patch uses reg_names array to emit register names, rather than have
knowledge scattered throughout the PTX backend. Also, converted
write_fn_proto_from_insn to use (renamed) write_arg_mode and (new)
write_return_mode. I also noticed we can use liveness information to determine
whether an
> rtx_renumbered_equal_p considers two LABEL_REFs equivalent if they
> have the same next_real_insn, unfortunately next_real_insn doesn't ignore
> debug insns. It ignores BARRIERs/JUMP_TABLE_DATA insns too, which is IMHO
> not desirable either, so this patch uses next_nonnote_nondebug_insn instead
On Tue, Dec 15, 2015 at 4:07 PM, Matthew Wahab
wrote:
> On 10/12/15 10:49, Ramana Radhakrishnan wrote:
>>
>> On Mon, Dec 7, 2015 at 4:10 PM, Matthew Wahab
>> wrote:
>>>
>>> On 27/11/15 17:11, Matthew Wahab wrote:
On 27/11/15 13:44, Christophe Lyon wrote:
>>
>> On 26/11/15 16:02,
On Tue, 2015-12-15 at 15:13 +, Moore, Catherine wrote:
>
> HI Steve, The patch is OK. Will you please add a test case and repost?
> Thanks,
> Catherine
Here is the patch with a test case.
2015-12-15 Steve Ellcey
PR target/65604
* config/mips/mips.c (mips_output_division
On Tue, Dec 15, 2015 at 4:03 PM, Matthew Wahab
wrote:
> On 10/12/15 10:45, Ramana Radhakrishnan wrote:
>>
>> On Tue, Dec 8, 2015 at 7:45 AM, Christian Bruel
>> wrote:
>>>
>>> Hi Matthew,
On 26/11/15 16:01, Matthew Wahab wrote:
>
>
> Hello,
>
> This patch adds th
Hi,
due to recent discussion on the basic asm, and the special handling of
ASM_INPUT in ia64, I tried to build a bare-metal cross-compiler for ia64, but
that did not work, because it seems to be impossible to build it without having
a stdlib.h.
With the attached patch, I was finally able to bu
On Tue, Dec 15, 2015 at 09:51:15PM +0100, Eric Botcazou wrote:
> > rtx_renumbered_equal_p considers two LABEL_REFs equivalent if they
> > have the same next_real_insn, unfortunately next_real_insn doesn't ignore
> > debug insns. It ignores BARRIERs/JUMP_TABLE_DATA insns too, which is IMHO
> > not
This patch just makes convert_for_initialization() to avoid eagerly
decaying an array, function, etc if the type we're converting to is a
class type, so that the correct conversion constructor could be later be
selected in perform_implicit_conversion_flags().
Bootstrap + regtest in progress on x86
On 12/14/2015 08:55 PM, tbsaunde+...@tbsaunde.org wrote:
From: Trevor Saunders
Hi,
http://gcc.gnu.org/ml/gcc-patches/2015-12/msg00365.html reminded me I hadn't
gotten around to marking *-knetbsd and openbsd 2/3 obsolete as I offered to do
back in the spring.
I tested I could still build on x8
On 12/15/2015 02:13 PM, Jakub Jelinek wrote:
On Tue, Dec 15, 2015 at 09:51:15PM +0100, Eric Botcazou wrote:
rtx_renumbered_equal_p considers two LABEL_REFs equivalent if they
have the same next_real_insn, unfortunately next_real_insn doesn't ignore
debug insns. It ignores BARRIERs/JUMP_TABLE_DA
On 12/14/2015 01:14 PM, Jakub Jelinek wrote:
Hi!
rtx_renumbered_equal_p considers two LABEL_REFs equivalent if they
have the same next_real_insn, unfortunately next_real_insn doesn't ignore
debug insns. It ignores BARRIERs/JUMP_TABLE_DATA insns too, which is IMHO
not desirable either, so this p
On 12/15/2015 02:13 PM, Bernd Edlinger wrote:
Hi,
due to recent discussion on the basic asm, and the special handling of
ASM_INPUT in ia64, I tried to build a bare-metal cross-compiler for ia64, but
that did not work, because it seems to be impossible to build it without having
a stdlib.h.
W
On Tue, Dec 15, 2015 at 02:32:47PM -0700, Jeff Law wrote:
> On 12/14/2015 08:55 PM, tbsaunde+...@tbsaunde.org wrote:
> >From: Trevor Saunders
> >
> >Hi,
> >
> >http://gcc.gnu.org/ml/gcc-patches/2015-12/msg00365.html reminded me I hadn't
> >gotten around to marking *-knetbsd and openbsd 2/3 obsolet
On 12/15/2015 03:02 PM, Trevor Saunders wrote:
Can you mark interix as obsolete? It hasn't even built for a long time.
Sure, I can do that if you want, I just wasn't sure before you wanted
to.
Please do. I know we've been round and round on that one before, but
given it hasn't been buil
On 12/14/2015 05:53 PM, Martin Sebor wrote:
The C atomic_init macro is implemented in terms of simple assignment
to the atomic variable pointed to by its first argument. That's
inefficient since the variable under initialization must not be
accessed by other threads and assignment provides seque
On Tue, Dec 15, 2015 at 11:51:49AM -0500, David Malcolm wrote:
> When issuing diagnostics for _Static_assert, we currently ignore the
> location/range of the asserted expression, and instead use the
> location/range of the first token within it, which can be
> incorrect for compound expressions:
>
On 12/15/2015 09:51 AM, David Malcolm wrote:
When issuing diagnostics for _Static_assert, we currently ignore the
location/range of the asserted expression, and instead use the
location/range of the first token within it, which can be
incorrect for compound expressions:
error: expression in stat
On 12/14/2015 01:29 AM, Jan Beulich wrote:
On 11.12.15 at 21:40, wrote:
On 12/11/2015 12:28 AM, Jan Beulich wrote:
gcc/c/
2015-12-10 Jan Beulich
* c-fold.c (c_fully_fold_internal): Also emit shift count
warnings for vector types.
* c-typeck.c (build_binary_op): Like
On 12/14/2015 05:26 AM, James Greenhalgh wrote:
On Thu, Dec 03, 2015 at 03:07:43PM -0600, Evandro Menezes wrote:
On 11/20/2015 05:53 AM, James Greenhalgh wrote:
On Thu, Nov 19, 2015 at 04:04:41PM -0600, Evandro Menezes wrote:
On 11/05/2015 02:51 PM, Evandro Menezes wrote:
2015-11-05 Evandro
On 12/15/2015 06:25 PM, Kyrill Tkachov wrote:
Bootstrapped and tested on arm, aarch64, x86_64.
I'd say let's wait. Some of the changes look misindented btw.
Bernd
On 12/15/2015 06:30 PM, Jiong Wang wrote:
You approved this patch at
https://gcc.gnu.org/ml/gcc-patches/2015-09/msg01722.html
under the condition that AArch64 cost on ccmp instruction should be
fixed first.
Wilco has fixed the cost issue in this patch set [3/4], and the
"XFAIL
On 12/11/2015 03:05 AM, Richard Biener wrote:
On Thu, Dec 10, 2015 at 9:08 PM, Jeff Law wrote:
On 12/03/2015 07:38 AM, Richard Biener wrote:
This pass is now enabled by default with -Os but has no limits on the
amount of
stmts it copies.
The more statements it copies, the more likely it is
On 12/15/2015 08:30 PM, David Malcolm wrote:
I got thinking about what we'd have to do to support Perforce-style
markers, and began to find my token-matching approach to be a little
clunky (in conjunction with reading Martin's observations on
c_parser_peek_nth_token).
Here's a reimplementation
On 12/15/2015 10:13 PM, Bernd Edlinger wrote:
due to recent discussion on the basic asm, and the special handling
of ASM_INPUT in ia64, I tried to build a bare-metal cross-compiler
for ia64, but that did not work, because it seems to be impossible to
build it without having a stdlib.h.
Actually
On 12/15/2015 06:20 PM, Wilco Dijkstra wrote:
Adding Bernd - would you mind reviewing the ccmp.c change please?
Oh sorry, didn't realize there was one in here as well. Looks ok.
Bernd
This is a collection of 4 bug fix patches for arc. All 4 patches are
really stand-alone, I've only grouped them together as they all only
effect arc.
I don't have write access to the GCC repository, so if they get
approved could they also be applied please.
Thanks,
Andrew
--
Andrew Burgess (4)
The use of the arc specific predicate store_update_operand is broken,
this commit fixes the error, and in the process removes the need for
store_update_operand altogether.
Currently store_update_operand is used with match_operator, the
store_update_operand checks that the operand is a MEM operand,
The use of the arc specific predicate load_update_operand is broken,
this commit fixes the error, and in the process removes the need for
load_update_operand altogether.
Currently load_update_operand is used with match_operator, the
load_update_operand checks that the operand is a MEM operand, wit
Missing function declaration causes a warning, that results in test
failure.
gcc/testsuite/ChangeLog:
* gcc.target/arc/jump-around-jump.c (rtc_set_time): Declare.
---
gcc/testsuite/ChangeLog | 4
gcc/testsuite/gcc.target/arc/jump-around-jump.c | 2 +-
2 files
We currently call JUMP_LABEL_AS_INSN on a jump instruction that might
have SIMPLE_RETURN as it's jump label, this triggers the assertions as
SIMPLE_RETURN is of type rtx_extra, not rtx_insn.
This commit first calls JUMP_LABEL then uses ANY_RETURN_P to catch all
of the return style jump labels. Af
Richard Sandiford wrote:
> "Ulrich Weigand" writes:
> > The problem is not DImode LABEL_REFs, but rather VOIDmode LABEL_REFs when
> > matched against a match_operand:DI.
>
> It'd be good to fix this in a more direct way though, rather than
> hack around it. It's possible that the trick will stop
In the C frontend,
c_parser_postfix_expression
after parsing a primary expression passes "loc", the location of the
*first token* in that expression to
c_parser_postfix_expression_after_primary,
which thus discards any range information we had for primary
expressions containing more than one to
Hi,
this patch fixes an inconsistency seen in g++.dg/lto/20081125_0.C testcase
where we have same body alias of dtor. The alias is DECL_VIRTUAL while
the dtor itself is not. symtab_node::fixup_same_cpp_alias_visibility
copies DECL_VIRTUAL_P from the alias target dropping the flag that is wrong.
I
Hi,
On 15.12.2015 22:55, Jeff Law wrote:
> On 12/15/2015 02:13 PM, Bernd Edlinger wrote:
>> Hi,
>>
>> due to recent discussion on the basic asm, and the special handling
>> of ASM_INPUT in ia64, I tried to build a bare-metal cross-compiler
>> for ia64, but that did not work, because it seems to
Removed the member variables which are only used in scop_get_dependence. Instead
only maintaining the overall dependence. Passes regtest and bootstrap.
gcc/ChangeLog:
2015-12-15 hiraditya
* graphite-dependences.c (scop_get_dependences): Use local pointers.
*
graphite-isl-ast-
Passes bootstrap and regtest.
gcc/ChangeLog:
2015-12-15 hiraditya
* graphite-sese-to-poly.c (build_poly_sr): Use refs.
---
gcc/graphite-sese-to-poly.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/graphite-sese-to-poly.c b/gcc/graphite-sese-to-poly.c
in
Hi,
On 16.12.2015 00:55 Bernd Schmidt wrote:
> On 12/15/2015 10:13 PM, Bernd Edlinger wrote:
>> due to recent discussion on the basic asm, and the special handling
>> of ASM_INPUT in ia64, I tried to build a bare-metal cross-compiler
>> for ia64, but that did not work, because it seems to be impos
On Mon, Dec 14, 2015 at 04:08:32PM +0100, Ulrich Weigand wrote:
> Dominik Vogt wrote:
>
> > The attached patch enables using r1 to r4 as the literal pool base pointer
> > if
> > one of them is unused in a leaf function. The unpatched code supports only
> > r5
> > and r13.
>
> I don't think tha
Hi,
When analyzing code size regressions for AVR for top-of-trunk, I
found a few cases where aggresive inlining (by the middle-end)
of functions containing calls to memcpy was bloating up the code.
Turns out that the AVR backend has MOVE_MAX set to 4 (unchanged from the
original commit
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