Hi all,
This converts the preprocessor check for WORD_REGISTER_OPERATIONS into a
runtime one
in rtlanal.c.
Since this one was in combination with an "#if defined" and used to guard an
if-statement
I'd appreciate it if someone gave it a double-check that I dind't screw up the
intended
behaviour.
Bootstrapped and tested on arm, aarch64, x86_64.
Ok for trunk?
Thanks,
Kyrill
2015-12-15 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
* rtlanal.c (nonzero_bits1): Convert preprocessor check
for WORD_REGISTER_OPERATIONS to runtime check.
diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c
index f893bca0d0a17498c1b234492e4acff02cec6e84..ab49602b72984e336f01a6b13f94993af9e4b8f9 100644
--- a/gcc/rtlanal.c
+++ b/gcc/rtlanal.c
@@ -4540,13 +4540,14 @@ nonzero_bits1 (const_rtx x, machine_mode mode, const_rtx known_x,
nonzero &= cached_nonzero_bits (SUBREG_REG (x), mode,
known_x, known_mode, known_ret);
-#if WORD_REGISTER_OPERATIONS && defined (LOAD_EXTEND_OP)
+#ifdef LOAD_EXTEND_OP
/* If this is a typical RISC machine, we only have to worry
about the way loads are extended. */
- if ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND
- ? val_signbit_known_set_p (inner_mode, nonzero)
- : LOAD_EXTEND_OP (inner_mode) != ZERO_EXTEND)
- || !MEM_P (SUBREG_REG (x)))
+ if (WORD_REGISTER_OPERATIONS
+ && ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND
+ ? val_signbit_known_set_p (inner_mode, nonzero)
+ : LOAD_EXTEND_OP (inner_mode) != ZERO_EXTEND)
+ || !MEM_P (SUBREG_REG (x))))
#endif
{
/* On many CISC machines, accessing an object in a wider mode
