On Thu, Feb 16, 2012 at 7:26 PM, Aldy Hernandez wrote:
> On 02/16/12 12:04, Jakub Jelinek wrote:
>>
>> On Thu, Feb 16, 2012 at 11:46:33AM -0600, Aldy Hernandez wrote:
>>>
>>> #GOOD
>>> houston:/build/t2/gcc$ ./cc1 a.c -fgnu-tm -O0 -quiet -w
>>> In function 'asmfunc',
>>> inlined from 'f' at a.
On Mon, Feb 20, 2012 at 10:56:30AM +0100, Richard Guenther wrote:
> Disabling early inlining for TM is a hack, I don't think you want to make
> people pay the optimizing penalty just because of asm diagnostics.
Yeah, it is unfortunate that without -g the diagnostic will be less verbose,
but even f
On Fri, Feb 17, 2012 at 2:50 PM, Jakub Jelinek wrote:
> Hi!
>
> The following testcase is miscompiled (by CCP, or, if -fno-tree-ccp,
> by VRP), because the (X & C1) | C2 folding changes the C1 constant
> into an integer constant with most significant bit set, but not
> sign-extended into the doubl
On Fri, Feb 17, 2012 at 2:51 PM, Rainer Orth
wrote:
> Rainer Orth writes:
>
>> Richard Guenther writes:
>>
>>> I'm not sure about the varasm.c change - it's definitely not a no-op
>>> (callback will be not set, and the flags will be different). Certainly
>>
>> As I've demonstrated in my respons
On Fri, Feb 17, 2012 at 02:01:36AM -0200, Alexandre Oliva wrote:
> for gcc/ChangeLog
> from Alexandre Oliva
>
> PR debug/52001
> * cselib.c (preserve_only_constants): Rename to...
> (preserve_constants_and_equivs): ... this. Split out...
> (invariant_or_equiv_p): ... th
On Fri, Feb 17, 2012 at 9:51 PM, Thomas Schwinge
wrote:
> Hi!
>
> How do we move this issue forward?
>
> On Mon, 23 Jan 2012 15:46:34 +0100, Bernd Schmidt
> wrote:
>> On 11/29/2011 05:35 PM, Mitchell, Mark wrote:
>> >>> So, I still think this patch is the best way to go forward, and it
>> >> doe
Hello Gerald,
Thank you for reviewing the earlier patch.
PFA, the patch modified as per your suggestion.
I have also attached here another patch for contrib.texi file changes.
Please let me know if any modifications are required in it.
Thanks and Regards,
Jayant Sonar
[KPIT Cummins, Pune]
cr
http://gcc.gnu.org/viewcvs?view=revision&revision=184393
http://gcc.gnu.org/viewcvs?view=revision&revision=184394
Index: gcc.c-torture/execute/pr52286.c
===
--- gcc.c-torture/execute/pr52286.c (revision 184393)
+++ gcc.c-torture/e
This fixes PR52298, we need to use the proper DR step for outer
loop vectorization.
Bootstrapped and tested on x86_64-unknown-linux-gnu, applied to trunk.
Richard.
2012-02-20 Richard Guenther
PR tree-optimization/52298
* tree-vect-stmts.c (vectorizable_store): Properly use
Hello,
> Hey, Jing, you broke the google/gcc-4_6 branch by checking the new
> header file into the wrong directory.
>
> Fixed via r184386.
>
google/gcc-4_6_2-mobile branch still has the same problem. Could
please someone fix it?
Thanks
Ilya
> Ollie
>
> On Fri, Feb 17, 2012 at 10:25 PM, Jing Yu
On Mon, Feb 20, 2012 at 04:11:13PM +0100, Richard Guenther wrote:
> This fixes PR52298, we need to use the proper DR step for outer
> loop vectorization.
>
> Bootstrapped and tested on x86_64-unknown-linux-gnu, applied to trunk.
Thanks.
> *** vectorizable_load (gimple stmt, gimple_s
Ping.
>>looks like an invalid transformation, but I suspect rather than setting
>>the CC register, the (*) insn is setting a pseudo (more accurate RTL
>>would be useful). There are some cases in ifcvt.c which check
>>targetm.small_register_classes_for_mode already, this is probably what
>>should be
On Sat, Feb 18, 2012 at 1:54 AM, Jakub Jelinek wrote:
> On Fri, Feb 17, 2012 at 05:20:02PM -0800, H.J. Lu wrote:
>> This patch backports the fix from trunk:
>>
>> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46770
>>
>> for google/gcc-4_6_2-mobile branch. This is needed to support C++
>> global co
The following patches don't depend on each other but are all for the
gl_wt TM method.
patch1:
For memory transfers from source regions with the read-for-write
modifier, undo logging of these regions was missing. Also optimize the
number of accesses to gtm_thr().
patch2:
Similar to the ml_wt code
On 02/20/2012 12:14 PM, Richard Guenther wrote:
> On Fri, Feb 17, 2012 at 9:51 PM, Thomas Schwinge
> wrote:
>> Hi!
>>
>> How do we move this issue forward?
>>
>> On Mon, 23 Jan 2012 15:46:34 +0100, Bernd Schmidt
>> wrote:
>>> That was committed a while ago. The part in stor-layout.c that stops u
On Thu, Feb 16, 2012 at 5:06 PM, Kirill Yukhin wrote:
> Hello guys,
> Here is a patch which adds support of first part of Intel TSX extensions.
>
> Could you please have a look?
As the first remark, you don't have to add BLKmode memory clobbers.
unspec_volatile RTX is considered to use and clobbe
Hi,
The patch (http://gcc.gnu.org/bugzilla/attachment.cgi?id=26585)
attached to the bug
(http://gcc.gnu.org/bugzilla/show_bug.cgi?id=52137) recovers
performance regressions for AMD's bdver2 processor.
It passes bootstrap and make check on x86_64.
The patch is simple and seems to have little risk
Hi,
thus, this is what I'm going to commit to resolve the issue (see audit
trail for details).
Tested x86_64-linux.
Thanks,
Paolo.
///
2012-12-20 Paolo Carlini
PR libstdc++/52241
* src/c++98/tree.cc (local_Rb_tree_increment,
local_Rb_tree_decre
On 20/02/12 17:28, Bernd Schmidt wrote:
> On 02/20/2012 12:14 PM, Richard Guenther wrote:
>> On Fri, Feb 17, 2012 at 9:51 PM, Thomas Schwinge
>> wrote:
>>> Hi!
>>>
>>> How do we move this issue forward?
>>>
>>> On Mon, 23 Jan 2012 15:46:34 +0100, Bernd Schmidt
>>> wrote:
That was committed
On 02/20/2012 06:39 PM, Richard Earnshaw wrote:
> I'm not sure why it should be. Can't a user write
>
> #ifdef __cplusplus
> #define BOOL bool
> #else
> #define bool _Bool
> #endif
>
> struct x {
> volatile BOOL a : 1;
> volatile BOOL b : 1;
> volatile unsigned char c : 6;
> volatile BOO
On Thu, Feb 16, 2012 at 5:47 PM, Jakub Jelinek wrote:
> On Thu, Feb 16, 2012 at 11:26:53AM -0500, Patrick Marlier wrote:
>> On 02/16/2012 11:06 AM, Kirill Yukhin wrote:
>> > +(define_insn "xbegin_1"
>> > + [(set (match_operand:SI 0 "register_operand" "=a")
>> > + (unspec_volatile:SI [(match_du
On Mon, Feb 20, 2012 at 07:10:26PM +0100, Uros Bizjak wrote:
> > So the above is right and needed, though perhaps we might want
> > a combine pattern or peephole to turn the
> > movl $-1, %eax
> > xbegin .+6
> > cmpl %eax, $-1
> > jne 1f
>
> The compiler can reverse the condition and exchange arms
On Mon, Feb 20, 2012 at 7:18 PM, Jakub Jelinek wrote:
> On Mon, Feb 20, 2012 at 07:10:26PM +0100, Uros Bizjak wrote:
>> > So the above is right and needed, though perhaps we might want
>> > a combine pattern or peephole to turn the
>> > movl $-1, %eax
>> > xbegin .+6
>> > cmpl %eax, $-1
>> > jne 1
On Mon, Feb 20, 2012 at 07:27:48PM +0100, Uros Bizjak wrote:
> IIUC the documentation, the fallback label is a parameter to xbegin
> insn, but the insn itself doesn't jump anywhere - it just records the
> parameter as a fallback address. However, there is no guarantee that
> the fallback code is ex
On Mon, Feb 20, 2012 at 7:31 PM, Jakub Jelinek wrote:
> On Mon, Feb 20, 2012 at 07:27:48PM +0100, Uros Bizjak wrote:
>> IIUC the documentation, the fallback label is a parameter to xbegin
>> insn, but the insn itself doesn't jump anywhere - it just records the
>> parameter as a fallback address. H
On 02/20/12 08:54, Torvald Riegel wrote:
> The following patches don't depend on each other but are all for the
> gl_wt TM method.
>
> patch1:
> For memory transfers from source regions with the read-for-write
> modifier, undo logging of these regions was missing. Also optimize the
> number of ac
On 02/20/12 10:35, Uros Bizjak wrote:
> On Mon, Feb 20, 2012 at 7:31 PM, Jakub Jelinek wrote:
>> On Mon, Feb 20, 2012 at 07:27:48PM +0100, Uros Bizjak wrote:
>>> IIUC the documentation, the fallback label is a parameter to xbegin
>>> insn, but the insn itself doesn't jump anywhere - it just record
On Mon, Feb 20, 2012 at 7:43 PM, Richard Henderson wrote:
IIUC the documentation, the fallback label is a parameter to xbegin
insn, but the insn itself doesn't jump anywhere - it just records the
parameter as a fallback address. However, there is no guarantee that
the fallback
On 02/20/12 10:51, Uros Bizjak wrote:
> On Mon, Feb 20, 2012 at 7:43 PM, Richard Henderson wrote:
>
> IIUC the documentation, the fallback label is a parameter to xbegin
> insn, but the insn itself doesn't jump anywhere - it just records the
> parameter as a fallback address. However,
On 02/20/2012 01:51 PM, Uros Bizjak wrote:
On Mon, Feb 20, 2012 at 7:43 PM, Richard Henderson wrote:
IIUC the documentation, the fallback label is a parameter to xbegin
insn, but the insn itself doesn't jump anywhere - it just records the
parameter as a fallback address. However, there is no g
On Mon, Feb 20, 2012 at 7:57 PM, Richard Henderson wrote:
tempRIP = RIP + SignExtend (IMM),
where RIP is instruction following XBEGIN instruction.
>>>
>>> So? .+N is generic assembler syntax, not specifying IMM=6.
>>> With "xbegin .+6" the assembler will of course encode IMM=0,
>>
On Mon, Feb 20, 2012 at 6:38 PM, Quentin Neill
wrote:
> Hi,
>
> The patch (http://gcc.gnu.org/bugzilla/attachment.cgi?id=26585)
> attached to the bug
> (http://gcc.gnu.org/bugzilla/show_bug.cgi?id=52137) recovers
> performance regressions for AMD's bdver2 processor.
>
> It passes bootstrap and mak
On Monday 9 January 2012 10:05:08 Richard Guenther wrote:
> Since GCC 4.4 applying the malloc attribute to realloc-like
> functions does not work under the documented constraints because
> the contents of the memory pointed to are not properly transfered
> from the realloc argument (or treated as p
Hi,
this patch fixes for mingw target gthread-linking issues about
weak-symbols. The issue is that pe-coff's weak support is partial
present, but it isn't fully compatible to ELF-version. For static
libraries it works in this case equivalent, but for shared (DLL)
version it doesn't. Therefore i
Hi,
this patch fixes an issue about libgcc config.host for SjLj variant build.
ChangeLog
2012-02-20 Kai Tietz
* config.host (i686-*-mingw*): Set md_unwind_header only for dw2-mode to
w32-unwind.h header.
Tested for i686-w64-migw32. Ok for apply?
Regards,
Kai
Index: config
On 02/20/12 12:37, Kai Tietz wrote:
> 2012-02-20 Kai Tietz
>
> * config.host (i686-*-mingw*): Set md_unwind_header only for dw2-mode
> to
> w32-unwind.h header.
Ok.
r~
On Mon, 2012-02-20 at 10:36 -0800, Richard Henderson wrote:
> On 02/20/12 08:54, Torvald Riegel wrote:
> > The following patches don't depend on each other but are all for the
> > gl_wt TM method.
> >
> > patch1:
> > For memory transfers from source regions with the read-for-write
> > modifier, un
Hi!
If processing_template_decl || processing_specialization,
check_literal_operator_args doesn't initialize *long_long_unsigned_p nor
*long_double_p, but the caller might use those.
Fixed thusly, bootstrapped/regtested on x86_64-linux and i686-linux
plus tested the PR testcase under valgrind, ok
On 02/20/12 12:14, Kai Tietz wrote:
> 2012-02-20 Kai Tietz
>
> PR libstdc++/52300
>* gthr.h (GTHREAD_USE_WEAK): Define as zero for mingw.
Ok.
r~
For C6X, I added a patch to separate out a REG_WORDS_BIG_ENDIAN macro
from WORDS_BIG_ENDIAN. Since the patch was originally for 4.5, it missed
a few new instances in IRA where we need to change which macro we use.
The following patch makes big-endian kernels boot.
Bootstrapped and regression teste
On 02/20/12 03:56, Richard Guenther wrote:
On Thu, Feb 16, 2012 at 7:26 PM, Aldy Hernandez wrote:
On 02/16/12 12:04, Jakub Jelinek wrote:
On Thu, Feb 16, 2012 at 11:46:33AM -0600, Aldy Hernandez wrote:
#GOOD
houston:/build/t2/gcc$ ./cc1 a.c -fgnu-tm -O0 -quiet -w
In function 'asmfunc',
On Mon, Feb 20, 2012 at 1:51 PM, Richard Guenther
wrote:
> On Mon, Feb 20, 2012 at 6:38 PM, Quentin Neill
> wrote:
>> Hi,
>>
>> The patch (http://gcc.gnu.org/bugzilla/attachment.cgi?id=26585)
>> attached to the bug
>> (http://gcc.gnu.org/bugzilla/show_bug.cgi?id=52137) recovers
>> performance reg
On 02/17/12 04:15, Kai Tietz wrote:
> 2012-02-17 Kai Tietz
>
> PR target/52238
> * stor-layout.c (place_field): Handle desired_align for
> ms-bitfields, too.
>
> 2012-02-17 Kai Tietz
>
> * gcc.dg/bf-ms-layout-3.c: New testcase.
As I mentioned on IRC, please use the
2012/2/20 Richard Henderson :
> On 02/17/12 04:15, Kai Tietz wrote:
>> 2012-02-17 Kai Tietz
>>
>> PR target/52238
>> * stor-layout.c (place_field): Handle desired_align for
>> ms-bitfields, too.
>>
>> 2012-02-17 Kai Tietz
>>
>> * gcc.dg/bf-ms-layout-3.c: New testcase.
Hello,
Two changes in the attached patch:
1. Remove a broken link for XScale documentation
2. Change some links to the C++ ABI (CodeSourcery -> Mentor)
Is this OK?
Ciao!
Steven
Index: readings.html
===
RCS file: /cvs/gcc/wwwdocs/ht
On Mon, Feb 20, 2012 at 11:26 PM, Steven Bosscher wrote:
> Hello,
>
> Two changes in the attached patch:
>
> 1. Remove a broken link for XScale documentation
> 2. Change some links to the C++ ABI (CodeSourcery -> Mentor)
One more: MeP is also gone...
Index: readings.html
On 02/20/12 13:16, Aldy Hernandez wrote:
> PR middle-end/52141
> * trans-mem.c (ipa_tm_scan_irr_block): Error out on GIMPLE_ASM's
> in a transaction safe function.
Ok.
r~
On Mon, 20 Feb 2012, Steven Bosscher wrote:
> Two changes in the attached patch:
>
> 1. Remove a broken link for XScale documentation
> 2. Change some links to the C++ ABI (CodeSourcery -> Mentor)
>
> Is this OK?
Sure thing. Just go for changes like this -- for web pages we
can interpret the ob
On Mon, 20 Feb 2012, Steven Bosscher wrote:
> 2. Change some links to the C++ ABI (CodeSourcery -> Mentor)
There was another one, which I just changes as well.
Gerald
Index: htdocs/faq.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/faq.
OK.
Jason
Hi,
this patch replaces use of "llx" for printf/scanf by inttypes.h
PRIxMAX/SCNxMAX macros. If those macros aren't present it defines
them as default to "llx".
ChangeLog
2012-02-20 Kai Tietz
PR lto/50616
* lto-plugin.c (PRIxMAX,SCNxMAX): Use inttypes.h header if
present, oth
Sorry -- I will fix it in google/gcc-4_6_2-mobile.
Thanks,
Jing
On Mon, Feb 20, 2012 at 7:15 AM, Ilya Enkovich wrote:
> Hello,
>
>> Hey, Jing, you broke the google/gcc-4_6 branch by checking the new
>> header file into the wrong directory.
>>
>> Fixed via r184386.
>>
>
> google/gcc-4_6_2-mobile
> IIUC the documentation, the fallback label is a parameter to xbegin
> insn, but the insn itself doesn't jump anywhere - it just records the
>From the point of view of the program XBEGIN behaves like a conditional
jump (with a very complicated and unpredictable condition)
-Andi
--
a...@linux.i
This is DJ's baby, let's see whether he has an alternate site?
(Google did not find me an immediate candidate.)
Gerald
On Mon, 20 Feb 2012, Steven Bosscher wrote:
> One more: MeP is also gone...
>
> Index: readings.html
> ===
> RCS
Hi!
This function spends significant amount of code to update the virtual
uses/defs in the new sequence, but only handles that way stores, not
non-pure/const calls, so we ICE during tree DSE on this testcase, because
vop has been marked for renaming.
Fixed thusly, bootstrapped/regtested on x86_64
> This is DJ's baby, let's see whether he has an alternate site?
Sorry, I got nothin'
Richard Henderson asked me to add an explanatory comments to explain
this decision.
* config/sparc/sparc.md (load_pcrel_sym): Explain why we
don't use the "rd %pc" instruction on v9 for PIC register loads.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@184422
138bc75d-0d04-0410
Hello!
I'm new to GCC internals, but I'm using GCC for couple of years.
Yesterday I found that GCC does not support calling SWI routines from C/C++
code.
For example, in other ARM-targeted compiliers developer can use such syntax
for function prototype:
In ARM IAR:
#pragma swi_number=0x15
int some_
Hi H.J.,
I think the patch itself is not enough.
I compared "AC_DEFUN([gcc_AC_INITFINI_ARRAY]" part (in acinclude.m4)
of gcc trunk and google/gcc-4_6_2-mobile, and found how
enable_initfini_array is
configured is different.
The patch breaks some of our tests. enable_initfini_array should be
disab
Hello!
> 2012-02-20 Quentin Neill
>
> PR target/52137
> * gcc/config/i386/bdver1.md (bdver1_call, bdver1_push,
> bdver1_pop, bdver1_leave, bdver1_lea, bdver1_imul_DI, bdver1_imul,
> bdver1_imul_mem_DI, bdver1_imul_mem, bdver1_idiv, bdver1_idiv_mem,
> bdver1_str, bdver1_idire
On Tue, Feb 21, 2012 at 12:26 AM, Andi Kleen wrote:
>> IIUC the documentation, the fallback label is a parameter to xbegin
>> insn, but the insn itself doesn't jump anywhere - it just records the
>
> From the point of view of the program XBEGIN behaves like a conditional
> jump (with a very compli
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