Richard Henderson asked me to add an explanatory comments to explain
this decision.
* config/sparc/sparc.md (load_pcrel_sym<P:mode>): Explain why we
don't use the "rd %pc" instruction on v9 for PIC register loads.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@184422
138bc75d-0d04-0410-961f-82ee72b054a4
---
gcc/ChangeLog | 5 +++++
gcc/config/sparc/sparc.md | 4 ++++
2 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e12e596..df2419a 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2012-02-20 David S. Miller <[email protected]>
+
+ * config/sparc/sparc.md (load_pcrel_sym<P:mode>): Explain why we
+ don't use the "rd %pc" instruction on v9 for PIC register loads.
+
2012-02-20 Aldy Hernandez <[email protected]>
PR middle-end/52141
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index f70acd3..c0c1ef8 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -1352,6 +1352,10 @@
;; Load in operand 0 the (absolute) address of operand 1, which is a symbolic
;; value subject to a PC-relative relocation. Operand 2 is a helper function
;; that adds the PC value at the call point to register #(operand 3).
+;;
+;; Even on V9 we use this call sequence with a stub, instead of "rd %pc, ..."
+;; because the RDPC instruction is extremely expensive and incurs a complete
+;; instruction pipeline flush.
(define_insn "load_pcrel_sym<P:mode>"
[(set (match_operand:P 0 "register_operand" "=r")
--
1.7.6.401.g6a319
