Re: Re: [PATCH] RISC-V: Prevent speculative vsetvl insn scheduling

2025-02-12 Thread 钟居哲
>> vsetvl pass inserts based on needs of vector instructions. Yes. vector instructions should make use of scheduler which could minimize "vsetvli" insertion in VSETVL PASS. What I said is we should not involve "vsetvli" instruction (not vector instructions like vadd.vv) in scheduler. juzhe.zh.

Re: Re: [PATCH] RISC-V: Prevent speculative vsetvl insn scheduling

2025-02-12 Thread 钟居哲
VSETVL PASS is supposed to insert "vsetvli" into optimal place so "vsetvli" inserted by VSETVL PASS shouldn't involved into instruction scheduling. juzhe.zh...@rivai.ai From: Jeff Law Date: 2025-02-13 08:47 To: Edwin Lu; gcc-patches CC: gnu-toolchain; vineetg; juzhe.zhong Subject: Re: [PATCH]