>> Yeah, just noticed that myself. Anyway will do some more tests,
>> maybe my initial VLS analysis was somehow flawed.
You can check binop_vx_constraint-167.c ~ binop_vx_constraint-174.c
This patch is pre-approved if you change as my suggestion.
I am gonna sleep so I am not able to review again
>> I'm wondering whether the VLA modes in the iterator are correct.
>> Looks dubious to me but unsure, will need to create some tests
>> before continuing.
It must be correct. We already have test (intrinsic codes) for it.
>> What's the problem with those? We probably won't reach there
>> becaus
OK. Make sense。
LGTM as long as you remove all
GET_MODE_BITSIZE (GET_MODE_INNER (mode)) <= GET_MODE_BITSIZE (Pmode)
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-16 04:30
To: 钟居哲; gcc-patches; palmer; kito.cheng; Jeff Law
CC: rdapp.gcc
Subject: Re: [PATCH] RISC-V: Disallow 64-bit indexe
Could you show me the example ?
It's used by handling SEW = 64 on RV32. I don't know why this patch touch this
code.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-15 22:27
To: 钟居哲; gcc-patches; palmer; kito.cheng; Jeff Law
CC: rdapp.gcc
Subject: Re: [PATCH] RISC-V: Disallow 64-bit inde
