On Tue, 8 Aug 2023, Jeff Law wrote:
> > I wonder however why do we need so much more code, including the middle
> > end too, to support this ISA extension than we do for the very same set of
> > MIPSr6 instructions under ISA_HAS_SEL, hmm...
> Because it doesn't handle as many cases as we're hand
On 8/8/23 15:52, Maciej W. Rozycki wrote:
On Fri, 4 Aug 2023, Jeff Law via Gcc-patches wrote:
It's also something I kept meaning to resolve and your submission just gave me
the proper motivation to move zicond forward. The target specific bits you
did lined up perfectly with the community f
On Fri, 4 Aug 2023, Jeff Law via Gcc-patches wrote:
> It's also something I kept meaning to resolve and your submission just gave me
> the proper motivation to move zicond forward. The target specific bits you
> did lined up perfectly with the community feedback on the original VRULL
> implementa
On 8/4/23 03:29, Xiao Zeng wrote:
On Thu, Aug 03, 2023 at 01:20:00 AM Jeff Law wrote:
In the wrong two optimization modes, I only considered the
case of satisfying the ELSE branch, but in fact, like the correct
two optimization modes, I should consider the case of satisfying
both the THA
On Thu, Aug 03, 2023 at 01:20:00 AM Jeff Law wrote:
>
>
>
>So we're being a bit too aggressive with the .opt zicond patterns.
>
>
>> (define_insn "*czero.eqz..opt1"
>> [(set (match_operand:GPR 0 "register_operand" "=r")
>> (if_then_else:GPR (eq (match_operand:X 1 "regi
