Philipp Tomsich writes:
> Richard,
>
> On Wed, 3 Nov 2021 at 10:08, Richard Sandiford
> wrote:
>>
>> Philipp Tomsich writes:
>> > This adds support and a basic tuning model for the Ampere Computing
>> > "Ampere-1" CPU.
>> >
>> > The Ampere-1 implements the ARMv8.6 architecture in A64 mode and is
Richard,
On Wed, 3 Nov 2021 at 10:08, Richard Sandiford
wrote:
>
> Philipp Tomsich writes:
> > This adds support and a basic tuning model for the Ampere Computing
> > "Ampere-1" CPU.
> >
> > The Ampere-1 implements the ARMv8.6 architecture in A64 mode and is
> > modelled as a 4-wide issue (as wi
Philipp Tomsich writes:
> This adds support and a basic turning model for the Ampere Computing
> "Ampere-1" CPU.
>
> The Ampere-1 implements the ARMv8.6 architecture in A64 mode and is
> modelled as a 4-wide issue (as with all modern micro-architectures,
> the chosen issue rate is a compromise bet
