:06 AM
To: Li Xu ; gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; richard.guent...@gmail.com; tamar.christ...@arm.com;
juzhe.zh...@rivai.ai; Li, Pan2
Subject: Re: [PATCH 2/2] RISC-V: Add testcases for signed vector SAT_ADD IMM
form 1
On 5/19/25 2:42 AM, Li Xu wrote:
> From: xuli
>
>
On 5/19/25 2:42 AM, Li Xu wrote:
From: xuli
This patch adds testcase for form1, as shown below:
void __attribute__((noinline)) \
vec_sat_s_add_imm_##T##_fmt_1##_##INDEX (T *out, T *op_1, unsigned limit) \
{
Nit for tailing empty line as below, otherwise LGTM for RISC-V part.
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i8.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
+
+#in
