On 6/12/23 17:39, juzhe.zhong wrote:
I take this work which is very important for VLA SLP too. I will
support VLS after I finish VLA SLP.
OK. I think I'll mark Kito's patch as dropped and we'll wait for your
implementation in this space.
jeff
On 5/30/23 17:37, juzhe.zhong wrote:
Oh. I forgot we need vl/vtype regnum dependency. It seems extending vla
pattern with vls mode is unavoidable. So I think we can
define_insn_and _spit and split intructions after RA so that we can get
benefits from general rtl code patterns.
So you're
_ATTRIBUTE)
+ (set_attr "vl_op_idx" const_int 2)
+(set (attr "ta") (symbol_ref "riscv_vector::TAIL_ANY"))
+(set (attr "ma") (symbol_ref "riscv_vector::MASK_ANY"))
+ (set (attr "avl_type") (symbol_ref "riscv_vector::VLS_AVL&q
It's long mail but I think this should explain most high level concept
why I did this:
I guess I skipped too much story about the VLS-mode support; VLS-mode
support can be split into the middle-end and back-end.
# Middle-end
As Richard mentioned, those VLS types can be held by VLA-modes; for
exam
RGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI
"TARGET_VECTOR_ELEN_64")
(VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI
"TARGET_VECTOR_ELEN_64 && TARG
effreyalaw;
pan2.li
Subject: Re: Re: [PATCH] RISC-V: Basic VLS code gen for RISC-V
On Tue, May 30, 2023 at 11:17 AM juzhe.zh...@rivai.ai
wrote:
>
> In the future, we will definitely mixing VLA and VLS-vlmin together in a
> codegen and it will not cause any issues.
> For VLS-vlmin,
ches; palmer; kito.cheng; jeffreyalaw; pan2.li
> Subject: Re: [PATCH] RISC-V: Basic VLS code gen for RISC-V
> >>> but ideally the user would be able to specify -mrvv-size=32 for an
> >>> implementation with 32 byte vectors and then vector lowering would make
> >
One more note: we found a real case in spec 2006, SLP convert two 8
bit into int8x2_t, but the value has live across the function call, it
only need to save-restore 16 bit, but it become save-restore VLEN bits
because it using VLA mode in backend, you could imagine when VLEN is
larger, the performa
23-05-30 17:05
To: juzhe.zh...@rivai.ai; Richard Biener; Kito.cheng
CC: rdapp.gcc; gcc-patches; palmer; kito.cheng; jeffreyalaw; pan2.li
Subject: Re: [PATCH] RISC-V: Basic VLS code gen for RISC-V
>>> but ideally the user would be able to specify -mrvv-size=32 for an
>>> implementation w
(I am still on the meeting hell, and will be released very later,
apology for short and incomplete reply, and will reply complete later)
One point for adding VLS mode support is because SLP, especially for
those SLP candidate not in the loop, those case use VLS type can be
better, of cause using l
>>> but ideally the user would be able to specify -mrvv-size=32 for an
>>> implementation with 32 byte vectors and then vector lowering would make use
>>> of vectors up to 32 bytes?
>
> Actually, we don't want to specify -mrvv-size = 32 to enable vectorization on
> GNU vectors.
> You can take a l
th RVV vector-length >= 128 bits.
This is what this patch want to do.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-05-30 15:13
To: Kito Cheng
CC: gcc-patches; palmer; kito.cheng; juzhe.zhong; jeffreyalaw; rdapp.gcc;
pan2.li
Subject: Re: [PATCH] RISC-V: Basic VLS code gen
on CPU with vector length=128. However, LLVM can
run on any RVV CPU with vector length >= 128.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-30 15:27
To: Kito Cheng; gcc-patches; palmer; kito.cheng; juzhe.zhong; jeffreyalaw;
pan2.li
CC: rdapp.gcc
Subject: Re: [PATCH] RISC-V: B
Hi Kito,
> GNU vector extensions is widly used around this world, and this patch
> enable that with RISC-V vector extensions, this can help people
> leverage existing code base with RVV, and also can write vector programs in a
> familiar way.
>
> The idea of VLS code gen support is emulate VLS op
On Tue, May 30, 2023 at 8:07 AM Kito Cheng via Gcc-patches
wrote:
>
> GNU vector extensions is widly used around this world, and this patch
> enable that with RISC-V vector extensions, this can help people
> leverage existing code base with RVV, and also can write vector programs in a
> familiar w
Ok. LGTM as long as you change the patch as I suggested.
Thanks.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-30 14:51
To: juzhe.zh...@rivai.ai
CC: gcc-patches; palmer; kito.cheng; jeffreyalaw; Robin Dapp; pan2.li
Subject: Re: [PATCH] RISC-V: Basic VLS code gen for RISC-V
> >> /* Return true if MODE is true VLS mode. */
> >> bool
> >> vls_mode_p (machine_mode mode)
> >> {
> >> switch (mode)
> >> {
> >> case E_V4SImode:
> >> case E_V2DImode:
> >> case E_V8HImode:
> >> case E_V16QImode:
> >> return true;
> >> default:
> >> return
>> /* Return true if MODE is true VLS mode. */
>> bool
>> vls_mode_p (machine_mode mode)
>> {
>> switch (mode)
>> {
>> case E_V4SImode:
>> case E_V2DImode:
>> case E_V8HImode:
>> case E_V16QImode:
>> return true;
>> default:
>> return false;
>> }
>> }
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