Hi, Kito.
After consideration, I think extending VLS modes into VLA pattern is not a
wise choice now.
And I prefer everything to be pefect (Otherwise, I will rework the whole thing
in the future and it's wasting time).
So I have suggestions as follows:
First, add a new avl_type here:
enum avl_type
{
NONVLMAX,
VLMAX,
+ VLS_AVL,
};
Second, define SEW && VLMUL && RATIO for VLS modes:
(define_attr "sew" ""
(cond [(eq_attr "mode" "V16QI")
(const_int 8)
(eq_attr "mode" "V8HI")
(const_int 16)
(eq_attr "mode" "V4SI")
(const_int 32)
(eq_attr "mode" "V2DI")
(const_int 64)]
(const_int INVALID_ATTRIBUTE)))
(define_attr "vlmul" ""
(cond [(eq_attr "mode" "V16QI")
(symbol_ref "riscv_vector::get_vlmul(E_V16QImode)")
(eq_attr "mode" "V8HI")
(symbol_ref "riscv_vector::get_vlmul(E_V8HImode)")
(eq_attr "mode" "V4SI")
(symbol_ref "riscv_vector::get_vlmul(E_V4SImode)")
(eq_attr "mode" "V2DI")
(symbol_ref "riscv_vector::get_vlmul(E_V2DImode)")
....
For "get_vlmul", we should be careful:
Since V16QI should LMUL = 1 when TARGET_MIN_VLEN == 128,
LMUL = 1/2 when TARGET_MIN_VLEN == 256...
etc....
Third, I think for VLS modes, you can define VLS pattern like this:
For GET_MODE_NUNITS (mode).to_constant () < 32:
+(define_insn "<optab><mode>3"
+ [(set (match_operand:VLS 0 "register_operand" "=vr")
+ (any_int_binop_no_shift:VLS
+ (match_operand:VLS 1 "register_operand" "vr")
+ (match_operand:VLS 2 "register_operand" "vr")))]
+ "TARGET_VECTOR"
+ "v<insn>.vv\t%0,%1,%2"
+ [(set_attr "type" "<int_binop_insn_type>")
+ (set_attr "mode" "<MODE>")
+ (set_attr "merge_op_idx" const_int INVALID_ATTRIBUTE)
+ (set_attr "vl_op_idx" const_int INVALID_ATTRIBUTE)
+ (set (attr "ta") (symbol_ref "riscv_vector::TAIL_ANY"))
+ (set (attr "ma") (symbol_ref "riscv_vector::MASK_ANY"))
+ (set (attr "avl_type") (symbol_ref "riscv_vector::VLS_AVL"))])
For GET_MODE_NUNITS (mode).to_constant () >= 32:
+(define_insn "<optab><mode>3"
+ [(set (match_operand:VLS 0 "register_operand" "=vr")
+ (any_int_binop_no_shift:VLS
+ (match_operand:VLS 1 "register_operand" "vr")
+ (match_operand:VLS 2 "register_operand" "vr")))+ (clobber
(mactch_opearnd:SI 2 ....))]
+ "TARGET_VECTOR"
+ "v<insn>.vv\t%0,%1,%2"
+ [(set_attr "type" "<int_binop_insn_type>")
+ (set_attr "mode" "<MODE>")
+ (set_attr "merge_op_idx" const_int INVALID_ATTRIBUTE)
+ (set_attr "vl_op_idx" const_int 2)
+ (set (attr "ta") (symbol_ref "riscv_vector::TAIL_ANY"))
+ (set (attr "ma") (symbol_ref "riscv_vector::MASK_ANY"))
+ (set (attr "avl_type") (symbol_ref "riscv_vector::VLS_AVL"))])
Then, with some minor tricks in VSETVL PASS (in "parse_insn" function), I think
it should work and this is the real optimal solution for
VLS modes auto-vectorizaiton.
Thanks.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-30 23:45
To: juzhe.zh...@rivai.ai
CC: Richard Biener; Robin Dapp; Kito.cheng; gcc-patches; palmer; jeffreyalaw;
pan2.li
Subject: Re: Re: [PATCH] RISC-V: Basic VLS code gen for RISC-V
It's long mail but I think this should explain most high level concept
why I did this:
I guess I skipped too much story about the VLS-mode support; VLS-mode
support can be split into the middle-end and back-end.
# Middle-end
As Richard mentioned, those VLS types can be held by VLA-modes; for
example, int32x4_t can be held by VNx4SI mode, so IMO there are three
different options here: 1) use VLS type with VLS mode in middle-end,
2) use VLS type with VLA mode in middle-end 3) use VLA type with VLA
mode.
Option 2 might be weird and not natural to implement in GCC, so let me
ignore that.
Option 3 is a possible way, and actually, I did that on our downstream
compiler, and then...we found a fact that is not friendly to
optimization; give a few practical examples here VLA type is hard to
present a vector constructor other than a step or splat/duplicated
value, we need to push those value into memory first - and then load
by len_load, okay, so constant propagation and folding can't work well
here - since it's hard to evaluate that with unknown vector length.
And it is also not friendly to pointer alias - because the length is
unknown, so GCC must be conservative on this, which will block some
optimization due to AA issues.
So IMO the use the VLS-type with VLS mode is the best way in the middle-end.
# Back-end
OK, it's back-end time; we have two options in the back-end to support
the VLS-type: support that with VLS mode or VLA mode.
What's the meaning of support with VLA mode? convert VLS-type stuff
into VLA mode pattern and give the right length information - then
everything works.
But what is wrong with this path? Again, similar issues in the
back-end: the propagation and folding with constant vector will be
limited when we hold in VLA type - we can't be held const_vector other
than splat/duplicated value or step value; it can't even be held
during the combine process, give an example here, we have a = {1, 2,
3, 4} and b = {4, 3, 2, 1}, this can be easily present at VLS mode
RTL, but impossible to present in VLA mode RLT, and then we can
folding to a+b to {5, 5, 5, 5}, but VLA mode will get a bunch of
problems to optimize those stuff.
And also the stack issue mentioned before - unless we can teach RA to
track the length used for each register with VLA mode, I believe it
would be terrible for RA...
# Back to this patch
Ju-Zhe has suggested we could reuse VLA pattern for VLS mode, I
considered that before, however, I feel that might not be friendly
with combine pass, because our VLA pattern is kind of complicated than
the plain VLS pattern, BUT I believe we will improve that in the near
future :P so I think that it should be reasonable just to use the same
pattern - then we could just add VLS mode to the mode iterator to
support that without magic mode changing, I can understand that really
seems very unsafe.
