Hi Jim,
On 13/11/15 17:53, Jim Wilson wrote:
Revised patch with the also missing xgene1 part added.
Jim
aprofile.patch
2015-11-13 Jim Wilson
* gcc/config/arm/t-aprofile (MULTILIB_MATCHES): Add lines for exynos-m1
and qdf24xx and xgene1 to match -march=armv8-a.
This is ok.
Revised patch with the also missing xgene1 part added.
Jim
2015-11-13 Jim Wilson
* gcc/config/arm/t-aprofile (MULTILIB_MATCHES): Add lines for exynos-m1
and qdf24xx and xgene1 to match -march=armv8-a.
Index: gcc/config/arm/t-aprofile
=
On Fri, Nov 13, 2015 at 9:02 AM, Kyrill Tkachov wrote:
> Sorry to chime in late on this, but while you're at it could
> you please add an xgene1 entry?
Yes, I just realized that xgene1 is missing too, I rushed the patch a
little too much. I will revise it to add xgene1 also.
Jim
Hi Jim,
On 13/11/15 16:59, Jim Wilson wrote:
On Thu, Nov 12, 2015 at 8:15 AM, Ramana Radhakrishnan
wrote:
This is OK to go in with a follow up to handle this cpu in t-aprofile
similar to the other cpus in there - for bonus points please deal with
the exynos core at the same time if not already
On Thu, Nov 12, 2015 at 8:15 AM, Ramana Radhakrishnan
wrote:
> This is OK to go in with a follow up to handle this cpu in t-aprofile
> similar to the other cpus in there - for bonus points please deal with
> the exynos core at the same time if not already done.
This was tested with a arm-eabi cro
On Wed, Nov 11, 2015 at 6:34 PM, Jim Wilson wrote:
> This adds an option for the Qualcomm server parts, qdf24xx, just
> optimizing like a cortex-a57 for now, same as how the initial Samsung
> exynos-m1 support worked.
>
> This was tested with armv8 and aarch64 bootstraps and make check.
>
> I had
On Wed, Nov 11, 2015 at 10:34:53AM -0800, Jim Wilson wrote:
> This adds an option for the Qualcomm server parts, qdf24xx, just
> optimizing like a cortex-a57 for now, same as how the initial Samsung
> exynos-m1 support worked.
>
> This was tested with armv8 and aarch64 bootstraps and make check.
>
On Wed, Nov 11, 2015 at 10:34 AM, Jim Wilson wrote:
> I had to disable the cortex-a57 fma steering pass in the aarch64 port
> while testing the patch. A bootstrap for aarch64 configured
> --with-cpu=cortex-a57 gives multiple ICEs while building the stage1
> libstdc++. The ICEs are in scan_rtx_re
