On Wed, Nov 11, 2015 at 10:34:53AM -0800, Jim Wilson wrote: > This adds an option for the Qualcomm server parts, qdf24xx, just > optimizing like a cortex-a57 for now, same as how the initial Samsung > exynos-m1 support worked. > > This was tested with armv8 and aarch64 bootstraps and make check. > > I had to disable the cortex-a57 fma steering pass in the aarch64 port > while testing the patch. A bootstrap for aarch64 configured > --with-cpu=cortex-a57 gives multiple ICEs while building the stage1 > libstdc++. The ICEs are in scan_rtx_reg at regrename.c:1074. This > looks vaguely similar to PR 66785. > > I am also seeing extra make check failures due to ICEs with armv8 > bootstrap builds configured --with-cpu=cortex-a57, I see ICEs in > scan_rtx_reg in regrename, and ICEs in decompose_normal_address in > rtlanal.c. The arm port doesn't have the fma steering support, which > seems odd, and is maybe a bug, so it isn't clear what is causing this > problem. > > I plan to look at these aarch64 and armv8 failures next, including PR > 66785. None of these have anything to do with my patch, as they > trigger for cortex-a57 which is already supported.
The bootstrap bugs should be fixed on trunk as of: http://gcc.gnu.org/viewcvs/gcc?view=revision&revision=230149 The AArch64 parts are OK, but the ARM parts look to be missing a hunk to gcc/config/arm/t-aprofile (and I can't approve those anyway). Thanks, James > Index: gcc/ChangeLog > =================================================================== > --- gcc/ChangeLog (revision 230118) > +++ gcc/ChangeLog (working copy) > @@ -1,3 +1,13 @@ > +2015-11-10 Jim Wilson <jim.wil...@linaro.org> > + > + * config/aarch64/aarch64-cores.def (qdf24xx): New. > + * config/aarch64/aarch64-tune.md: Regenerated. > + * config/arm/arm-cores.def (qdf24xx): New. > + * config/arm/arm-tables.opt, config/arm/arm-tune.md: Regenerated. > + * config/arm/bpabi.h (BE8_LINK_SPEC): Add qdf24xx support. > + * doc/invoke.texi (AArch64 Options/-mtune): Add "qdf24xx". > + (ARM Options/-mtune); Likewise.
