On Tue, Dec 06, 2016 at 03:10:50PM +, Wilco Dijkstra wrote:
>
>
> ping
OK.
This has been on the list since before Stage 1 closed and should be low
risk outside of code using the SHA1H intrinsics.
Though, given where we are in the release cycle, please give
Richard/Marcus 24 hours to ob
Wilco Dijkstra wrote:
> James Greenhalgh wrote:
>
> > I haven't seen a follow-up to Andrew's point regarding other
> > read-modify-write operations.
> >
> > Did youi investigate the cost of these?
>
> I looked at whether there are other similar cases, but it appears SHA1
> is unique due to the odd
James Greenhalgh wrote:
> I haven't seen a follow-up to Andrew's point regarding other
> read-modify-write operations.
>
> Did youi investigate the cost of these?
I looked at whether there are other similar cases, but it appears SHA1
is unique due to the odd dataflow, the mismatch in latencies a
On Tue, Dec 06, 2016 at 03:10:50PM +, Wilco Dijkstra wrote:
>
>
> ping
I haven't seen a follow-up to Andrew's point regarding other
read-modify-write operations.
Did youi investigate the cost of these?
James
>
>
> From: Wilco Dijkstra
> Sent: 25 October 2016 18:08
> To: GCC Patches
ping
From: Wilco Dijkstra
Sent: 25 October 2016 18:08
To: GCC Patches
Cc: nd
Subject: [PATCH][AArch64] Improve SHA1 scheduling
SHA1H instructions may be scheduled after a SHA1C instruction
that uses the same input register. However SHA1C updates its input,
so if SHA1H is scheduled aft
ping
From: Wilco Dijkstra
Sent: 25 October 2016 18:08
To: GCC Patches
Cc: nd
Subject: [PATCH][AArch64] Improve SHA1 scheduling
SHA1H instructions may be scheduled after a SHA1C instruction
that uses the same input register. However SHA1C updates its input,
so if SHA1H is scheduled after it
Andrew Pinski wrote:
> On Tue, Oct 25, 2016 at 10:08 AM, Wilco Dijkstra
> wrote:
> > SHA1H instructions may be scheduled after a SHA1C instruction
> > that uses the same input register. However SHA1C updates its input,
> > so if SHA1H is scheduled after it, it requires an extra move.
> > Increas
On Tue, Oct 25, 2016 at 10:08 AM, Wilco Dijkstra wrote:
> SHA1H instructions may be scheduled after a SHA1C instruction
> that uses the same input register. However SHA1C updates its input,
> so if SHA1H is scheduled after it, it requires an extra move.
> Increase the priority of SHA1H to ensure
ping
From: Wilco Dijkstra
Sent: 25 October 2016 18:08
To: GCC Patches
Cc: nd
Subject: [PATCH][AArch64] Improve SHA1 scheduling
SHA1H instructions may be scheduled after a SHA1C instruction
that uses the same input register. However SHA1C updates its input,
so if SHA1H is scheduled after it
