Andrew Pinski wrote: > On Tue, Oct 25, 2016 at 10:08 AM, Wilco Dijkstra <wilco.dijks...@arm.com> > wrote: > > SHA1H instructions may be scheduled after a SHA1C instruction > > that uses the same input register. However SHA1C updates its input, > > so if SHA1H is scheduled after it, it requires an extra move. > > Increase the priority of SHA1H to ensure it gets scheduled > > earlier, avoiding the move. > > > > Is this something the generic scheduler could do automatically for > > instructions with RMW operands? > > I was thinking that but there are many of those on x86 so it might not > make sense at all. > Also the SIMD instruction FMLA has the similar problem most likely > though I don't know if it make sense to do a similar thing for that > one.
Indeed it doesn't always make sense. I've never seen the issue with FMLA for example, so maybe a more generic mechanism isn't required. > Maybe it makes sense to mark the instructions in the .md file with > some attribute and then just check for that attribute here instead of > special casing SHA1C. That should be possible if adding attributes is not expensive in terms of memory/compile time. Wilco
