Thanks for your review! I'll ask Hongtao to check-in the patch for me.
Uros Bizjak 于2020年10月29日周四 下午4:08写道：
>
> On Thu, Oct 29, 2020 at 7:52 AM Hongyu Wang wrote:
> >
> > Hi Uros,
> >
> > > is there a reason to introduce all these (with corresponding changes)?
> > > SSE options live in ISA bitma
On Thu, Oct 29, 2020 at 7:52 AM Hongyu Wang wrote:
>
> Hi Uros,
>
> > is there a reason to introduce all these (with corresponding changes)?
> > SSE options live in ISA bitmap, so it is kind of strange you need to
> > handle them in ISA2 bitmap. Option handling is not exactly my area,
> > please a
Hi Uros,
> is there a reason to introduce all these (with corresponding changes)?
> SSE options live in ISA bitmap, so it is kind of strange you need to
> handle them in ISA2 bitmap. Option handling is not exactly my area,
> please ask HJ to comment and review this part.
As Hongtao said, this par
On Wed, Oct 28, 2020 at 8:24 PM Uros Bizjak wrote:
>
> On Wed, Oct 28, 2020 at 10:54 AM Hongyu Wang wrote:
> >
> > Hi Uros,
> >
> > Thanks for the example. We've update the patterns with new expanders
> > and predicates like vzeroall.
> > Now the generated insn for "encodekey128u32" is like
> >
On Wed, Oct 28, 2020 at 10:54 AM Hongyu Wang wrote:
>
> Hi Uros,
>
> Thanks for the example. We've update the patterns with new expanders
> and predicates like vzeroall.
> Now the generated insn for "encodekey128u32" is like
>
> (insn 7 6 8 2 (parallel [
> (set (reg:SI 84 [ ])
>
Hi Uros,
Thanks for the example. We've update the patterns with new expanders
and predicates like vzeroall.
Now the generated insn for "encodekey128u32" is like
(insn 7 6 8 2 (parallel [
(set (reg:SI 84 [ ])
(unspec_volatile:SI [
(reg:SI 85)
On Wed, Oct 21, 2020 at 1:48 PM Uros Bizjak wrote:
>
> On Wed, Oct 21, 2020 at 11:11 AM Hongyu Wang wrote:
> >
> > Hi,
> >
> > > IIRC, adding a new regclass is O(n^2), so it should be avoided. I
> > > think that the new patterns should follow the same path as vzeroall
> > > and vzeroupper pattern
On Wed, Oct 21, 2020 at 11:11 AM Hongyu Wang wrote:
>
> Hi,
>
> > IIRC, adding a new regclass is O(n^2), so it should be avoided. I
> > think that the new patterns should follow the same path as vzeroall
> > and vzeroupper patterns, where we emit the pattern with explicit hard
> > regs.
> >
> > BT
Hi,
> IIRC, adding a new regclass is O(n^2), so it should be avoided. I
> think that the new patterns should follow the same path as vzeroall
> and vzeroupper patterns, where we emit the pattern with explicit hard
> regs.
>
> BTW: We do have SSE_FIRST_REG class, but this class was added to solve
>
Hello!
> This patch is about to support Intel Key Locker extension.
>
> Key Locker provides a mechanism to encrypt and decrypt data with an AES
key without having access to the raw key value.
>
> For more details, please refer to
https://software.intel.com/content/dam/develop/external/us/en/docume
Hongyu Wang 于2020年9月21日周一 下午1:30写道：
>
> Hi:
>
> This patch is about to support Intel Key Locker extension.
>
> Key Locker provides a mechanism to encrypt and decrypt data with an AES
key without having access to the raw key value.
>
> For more details, please refer to
https://software.intel.com/co
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