On 02/02/2018 09:17 AM, Richard Sandiford wrote:
Richard Sandiford writes:
Segher Boessenkool writes:
Hi!
On Fri, Jan 26, 2018 at 01:25:51PM +, Richard Sandiford wrote:
if (SCALAR_INT_MODE_P (inmode))
new_out_reg = gen_lowpart_SUBREG (outmode, reg);
else
On Fri, Feb 02, 2018 at 02:17:59PM +, Richard Sandiford wrote:
> Richard Sandiford writes:
> > Segher Boessenkool writes:
> >> On Fri, Jan 26, 2018 at 01:25:51PM +, Richard Sandiford wrote:
> >>> if (SCALAR_INT_MODE_P (inmode))
> >>> new_out_reg = gen_lowpart_SUBREG (outmode, re
Richard Sandiford writes:
> Segher Boessenkool writes:
>> Hi!
>>
>> On Fri, Jan 26, 2018 at 01:25:51PM +, Richard Sandiford wrote:
>>> if (SCALAR_INT_MODE_P (inmode))
>>> new_out_reg = gen_lowpart_SUBREG (outmode, reg);
>>> else
>>> - new_out_reg = gen_rtx_SUBREG (ou
Segher Boessenkool writes:
> Hi!
>
> On Fri, Jan 26, 2018 at 01:25:51PM +, Richard Sandiford wrote:
>>if (SCALAR_INT_MODE_P (inmode))
>> new_out_reg = gen_lowpart_SUBREG (outmode, reg);
>>else
>> -new_out_reg = gen_rtx_SUBREG (outmode, reg, 0);
>> +{
>>
On Mon, Jan 29, 2018 at 11:07:12PM -0700, Jeff Law wrote:
> OK. Makes me wonder how many big endian LRA targets are getting
> significant use.
powerpc and powerpc64 are BE, but we don't often have QImode and HImode
(all instructions work on 32-bit or 64-bit words).
Segher
Hi!
On Fri, Jan 26, 2018 at 01:25:51PM +, Richard Sandiford wrote:
> if (SCALAR_INT_MODE_P (inmode))
> new_out_reg = gen_lowpart_SUBREG (outmode, reg);
> else
> - new_out_reg = gen_rtx_SUBREG (outmode, reg, 0);
> + {
> + poly_uint64 offset =
> OK. Makes me wonder how many big endian LRA targets are getting significant
> use.
Debian still has an active SPARC64 port now based on GCC 7 with LRA.
--
Eric Botcazou
On 01/26/2018 06:25 AM, Richard Sandiford wrote:
> LRA was using a subreg offset of 0 whenever constraints matched
> two operands with different modes. That leads to an invalid offset
> (and ICE) on big-endian targets if one of the modes is narrower
> than a word. E.g. if a (reg:SI X) is matched
LRA was using a subreg offset of 0 whenever constraints matched
two operands with different modes. That leads to an invalid offset
(and ICE) on big-endian targets if one of the modes is narrower
than a word. E.g. if a (reg:SI X) is matched to a (reg:QI Y),
the big-endian subreg should be (subreg:
