Hi Guys,
I am applying the patch below to the RX's handling of vector
functions. The RX ABI specifies that small integer return values
should always be promoted to 32-bit values, but the code that performs
this promotion was also affecting vector types. This results in
internal compile
Hi Guys,
I am applying the patch below to enhance the RX backend so that it
will push and pop multiple groups of registers using the PUSHM and
POPM instructions, thus reducing code size and increasing
performance.
Cheers
Nick
gcc/ChangeLog
2015-05-28 Nick Clifton
* config/r
Hi Guys,
I am applying the attached patch to the RX backend. It adds a new
command line option -mno-allow-string-insns which stops the compiler
from using any of the RX string instructions (SMOVF, SUNTIL, etc).
These instructions are problematic because they are unsafe if used in
the RX
Hi Guys,
I am checking in the patch below to fix a small DWARF generation
problem with the RX backend. The stack_push pattern contains two
separate operations that act in parallel, but they were written as if
they happened in sequence. Which meant that the DWARF generated to
show where
Hi Guys,
I am checking in the patch below to fix a small typo in the
description of the RX vector function attribute.
Cheers
Nick
gcc/ChangeLog
2014-06-26 Nick Clifton
* doc/extend.texi (Function Attributes): Fix typo in description
of RX vector attribute.
Index: doc/e
Hi Guys,
I am applying the patch below to fix a small problem with the RX port
- it was using non-log based alignment values for jumps, loops and
labels when user specified alignment was enabled.
Cheers
Nick
gcc/ChangeLog
2014-06-13 Nick Clifton
* config/rx/rx.h (JUMP_ALIGN):
Hi Guys,
I am applying this patch to fix up a few issues with the RX backend.
With this patch applied there are 355 fewer gcc testsuite regressions.
Cheers
Nick
gcc/ChangeLog
2012-11-20 Nick Clifton
* config/rx/rx.c (rx_function_arg_boundary): When using the RX ABI
alig
On Wed, 3 Oct 2012, Nick Clifton wrote:
> PS. I have even remembered to include a patch to the html
> documentation as well!
Yes, I was going to mention this appreciatively. ;-)
A minor change I applied on top is the following, adding a closing
and a dash in command-line.
Thanks,
Gerald
Index
Hi Guys,
I am applying the patch below to the RX backend. It adds support for
issuing warning messages when multiple fast interrupt routines are
defined in the same compilation unit. The RX only supports one fast
interrupt so it is probably a mistake to define more than one. If the
pr
Hi Guys,
I am checking in the patch below to the mainline and 4.7 branch
sources to fix a typo in the comparesi3_extend patterns in the rx.md
file. Operand 0 is an input operand but it had an = modifier applied
to it. This confused gcc's internals and resulted in several ICEs in
the gc
Hi Mike,
I plan on applying a similar patch to the mainline sources once I have
finished regression testing them.
Really, trunk should always go in first... Could you hold 4.7 until trunk goes
in?
Sorry, I had already checked the patch in. I have now checked in the
trunk patch, with o
On Jun 26, 2012, at 1:59 AM, Nick Clifton wrote:
> I am applying the patch below to the 4.7 branch. It fixes the
> simple_return pattern in the RX backend so that it uses the
> (simple_return) rtl. This fixes 59 gcc testsuite failures and
> introduces no regressions.
>
> I plan on applying
Hi Guys,
I am applying the patch below to the 4.7 branch. It fixes the
simple_return pattern in the RX backend so that it uses the
(simple_return) rtl. This fixes 59 gcc testsuite failures and
introduces no regressions.
I plan on applying a similar patch to the mainline sources once I
On 01/13/2012 04:31 AM, nick clifton wrote:
> Hi Richard,
>
>> Not an ideal solution, since the availability of this pattern implies
>> it's extremely cheap, and we'll replace jumps to the epilogue with
>> this pattern.
>> Or to define an availability predicate similar to i386, testing if
>> the e
Hi Guys,
As pointed out by Richard Henderson the new return pattern in the RX
backend should only be used when it is possible to return with just a
simple RTS instruction, so I am checking in the patch below to
implement this.
Cheers
Nick
gcc/ChangeLog
2012-01-17 Nick Clifton
Hi Richard,
Not an ideal solution, since the availability of this pattern implies
it's extremely cheap, and we'll replace jumps to the epilogue with
this pattern.
Or to define an availability predicate similar to i386, testing if
the epilogue is trivial, and only a return insn is needed.
Somet
On 01/11/2012 10:39 PM, Nick Clifton wrote:
> +(define_expand "return"
> + [(return)]
> + ""
> + "rx_expand_epilogue (false); DONE;"
> +)
Not an ideal solution, since the availability of this pattern implies
it's extremely cheap, and we'll replace jumps to the epilogue with
this pattern.
A hac
Hi Guys,
I am checking in the patch below to fix a problem building the RX
port. Targets that define the "simple_return" pattern must also
define a "return" pattern. Otherwise gcc/function.c will fail to
build.
Cheers
Nick
gcc/ChangeLog
2012-01-11 Nick Clifton
* config/rx
Hi Richard,
The SMIN pattern has the same problem.
*sigh* Fixed.
Cheers
Nick
On 10/05/2011 03:23 AM, Nick Clifton wrote:
> The final fix was pointed out by Richard Henderson. The recently
> added support for narrow mode min and max instructions did not work
> for the SMAX insn, as the RX does not have narrow mode versions of
> this insn.
The SMIN pattern has the s
Hi Guys,
I am applying the attached patch to add support for position
independent data to the RX backend. When this mode is enabled
constant data is referenced via an offset from a base address held in
a fixed register. This allows the position of this data to be
determined at run-time
Hi Guys,
I am applying the patch below to fix a couple of bugs in the RX's
machine description patterns. The first concerns the tablejump
pattern, which needs to include a label to be referenced by the
ASM_OUTPUT_ADDR_DIFF_ELT macro.
The second problem is the ADDDI3 spiltter which was
On 09/28/2011 07:34 AM, Nick Clifton wrote:
> -(define_insn "smaxsi3"
> - [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
> - (smax:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
> - (match_operand:SI 2 "rx_source_operand"
> -
Hi Guys,
I am going to apply the patch below to the RX backend to add support
for generating MIN and MAX instructions for HI and QI modes.
Cheers
Nick
gcc/ChangeLog
2011-09-28 Nick Clifton
* config/rx/predicates.md (rx_minmax_operand): New predicate.
Accepts immediates
Hi Guys,
I am applying the patch below to fix a couple of problems building
libgcc for the RX target. The first is that when 32-bit doubles are
enabled we need to make sure that we never try to construct a 64-bit
double type. This is done in rx-lib.h, but it was only being enabled
when
On 08/11/2011 05:19 AM, Nick Clifton wrote:
> Hi Guys,
>
> I am applying the patch below on behalf of Renesas. It adds support
> to the RX backend for conditional register moves.
>
> Tested without any regressions on an rx-elf toolchain.
>
> Cheers
> Nick
>
> gcc/ChangeLog
> 2011-08-11
Hi Guys,
I am applying the patch below on behalf of Renesas. It adds support
to the RX backend for conditional register moves.
Tested without any regressions on an rx-elf toolchain.
Cheers
Nick
gcc/ChangeLog
2011-08-11 Kazuhiro Inaoka
* config/rx/rx.md (movsicc): Allow reg
Hi Paul,
It disables the peephole optimizations in the rx.md file that combine a
load followed by a zero- or sign- extend operation. The disabling
only happens at -O3 (or higher) as although the peepholes reduce the
number of instructions they can introduce pipeline stalls that
actual
> I am checking in the patch below to the mainline and 4.6 branch. It
> disables the peephole optimizations in the rx.md file that combine a
> load followed by a zero- or sign- extend operation. The disabling
> only happens at -O3 (or higher) as although the peepholes reduce the
> number of
Hi Guys,
I am checking in the patch below to the mainline and 4.6 branch. It
disables the peephole optimizations in the rx.md file that combine a
load followed by a zero- or sign- extend operation. The disabling
only happens at -O3 (or higher) as although the peepholes reduce the
numbe
Hi Guys,
I am applying the patch below to fix a bug with the
rx_memory_move_cost function. The problem was that the costs are
meant to be relative to the cost of moving a value between registers,
but the existing definition was making stores cheaper than moves, and
loads the same cost a
Hi Guys,
I am applying the patch below to fix a minor discrepancy in the rx.md
file. Several patterns can only use restricted memory addresses.
They have the correct Q constraint, but they were using the more
permissive memory_operand predicate. The patch fixes these patterns
by replac
Hi Guys,
I am applying the patch below to add a couple of peephole
optimizations to the RX backend. It seems that GCC does not cope very
well with the RX's ability to perform either sign-extending loads or
zero-extending loads and so sometimes it can generate an extending
load followed
Hi Guys,
I am applying the patch below to add a peephole optimization to the RX
backend. It was suggested by Kazuhio Inaoka at Renesas Japan, and
adapted by me to use peephole2 system. It finds a register move
followed by a comparison of the moved register against zero and
replaces the
Hi Guys,
I am applying the patch below to the mainline and 4.6 branch sources.
It fixes a few GCC testsuite failures for the RX target, specifically:
gcc.dg/20020312-2.c
gcc.dg/pr28796-2.c
gcc.dg/torture/builtin-cproj-1.c
gcc.dg/torture/type-generic-1.c
gcc.target/rx/
Hi Guys,
I am applying the patch below to add alignment control for jumps,
loops and labels to the RX backend.
Tested without regressions on an rx-elf target.
Cheers
Nick
gcc/ChangeLog
2011-03-24 Nick Clifton
* config/rx/rx.h (LABEL_ALIGN_FOR_BARRIER): Define.
(ASM_O
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