On 8/16/23 02:33, Philipp Tomsich wrote:
Could we use the underlying 'fence' instruction (unless the assembler
rejects the specific form that is needed) instead of the hex-insn?
Should this also check HAVE_AS_MARCH_ZIHINTPAUSE (which must then also
be added to configure.ac)?
It seems reasona
On Wed, 16 Aug 2023 at 03:27, Jeff Law via Gcc-patches
wrote:
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>
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> On 8/9/23 20:25, Tsukasa OI wrote:
> > From: Tsukasa OI
> >
> > The "pause" RISC-V hint instruction requires the 'Zihintpause' extension
> > (in the assembler). However, GCC emits "pause" unconditionally, making
> > an assembl
On 8/9/23 20:25, Tsukasa OI wrote:
From: Tsukasa OI
The "pause" RISC-V hint instruction requires the 'Zihintpause' extension
(in the assembler). However, GCC emits "pause" unconditionally, making
an assembler error while compiling code with __builtin_riscv_pause while
the 'Zihintpause' exte
From: Tsukasa OI
The "pause" RISC-V hint instruction requires the 'Zihintpause' extension
(in the assembler). However, GCC emits "pause" unconditionally, making
an assembler error while compiling code with __builtin_riscv_pause while
the 'Zihintpause' extension disabled.
However, the "pause" in
