Got it, thanks Jeff.
Pan
-Original Message-
From: Jeff Law
Sent: Monday, August 26, 2024 10:21 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v3] RISC-V: Support IMM for operand 0 of ussub pattern
On
On 8/25/24 7:35 PM, Li, Pan2 wrote:
Thanks Jeff.
OK. I'm assuming we don't have to worry about the case where X is wider
than Xmode? ie, a DImode on rv32?
Yes, the DImode is disabled by ANYI iterator for ussub pattern.
Thanks. Just wanted to make sure. And for the avoidance of doubt, t
PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v3] RISC-V: Support IMM for operand 0 of ussub pattern
On 8/18/24 11:23 PM, pan2...@intel.com wrote:
> From: Pan Li
>
> This patch would like to allow IMM f
On 8/18/24 11:23 PM, pan2...@intel.com wrote:
From: Pan Li
This patch would like to allow IMM for the operand 0 of ussub pattern.
Aka .SAT_SUB(1023, y) as the below example.
Form 1:
#define DEF_SAT_U_SUB_IMM_FMT_1(T, IMM) \
T __attribute__((noinline)) \
sat_u_sub_imm##I
From: Pan Li
This patch would like to allow IMM for the operand 0 of ussub pattern.
Aka .SAT_SUB(1023, y) as the below example.
Form 1:
#define DEF_SAT_U_SUB_IMM_FMT_1(T, IMM) \
T __attribute__((noinline)) \
sat_u_sub_imm##IMM##_##T##_fmt_1 (T y) \
{
