Thanks Jeff.
> OK. I'm assuming we don't have to worry about the case where X is wider
> than Xmode? ie, a DImode on rv32?
Yes, the DImode is disabled by ANYI iterator for ussub pattern.
Pan
-----Original Message-----
From: Jeff Law <jeffreya...@gmail.com>
Sent: Sunday, August 25, 2024 11:22 PM
To: Li, Pan2 <pan2...@intel.com>; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp....@gmail.com
Subject: Re: [PATCH v3] RISC-V: Support IMM for operand 0 of ussub pattern
On 8/18/24 11:23 PM, pan2...@intel.com wrote:
> From: Pan Li <pan2...@intel.com>
>
> This patch would like to allow IMM for the operand 0 of ussub pattern.
> Aka .SAT_SUB(1023, y) as the below example.
>
> Form 1:
> #define DEF_SAT_U_SUB_IMM_FMT_1(T, IMM) \
> T __attribute__((noinline)) \
> sat_u_sub_imm##IMM##_##T##_fmt_1 (T y) \
> { \
> return (T)IMM >= y ? (T)IMM - y : 0; \
> }
>
> DEF_SAT_U_SUB_IMM_FMT_1(uint64_t, 1023)
>
> Before this patch:
> 10 │ sat_u_sub_imm82_uint64_t_fmt_1:
> 11 │ li a5,82
> 12 │ bgtu a0,a5,.L3
> 13 │ sub a0,a5,a0
> 14 │ ret
> 15 │ .L3:
> 16 │ li a0,0
> 17 │ ret
>
> After this patch:
> 10 │ sat_u_sub_imm82_uint64_t_fmt_1:
> 11 │ li a5,82
> 12 │ sltu a4,a5,a0
> 13 │ addi a4,a4,-1
> 14 │ sub a0,a5,a0
> 15 │ and a0,a4,a0
> 16 │ ret
>
> The below test suites are passed for this patch:
> 1. The rv64gcv fully regression test.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_gen_unsigned_xmode_reg): Add new
> func impl to gen xmode rtx reg from operand rtx.
> (riscv_expand_ussub): Gen xmode reg for operand 1.
> * config/riscv/riscv.md: Allow const_int for operand 1.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/sat_arith.h: Add test helper macro.
> * gcc.target/riscv/sat_u_sub_imm-1.c: New test.
> * gcc.target/riscv/sat_u_sub_imm-1_1.c: New test.
> * gcc.target/riscv/sat_u_sub_imm-1_2.c: New test.
> * gcc.target/riscv/sat_u_sub_imm-2.c: New test.
> * gcc.target/riscv/sat_u_sub_imm-2_1.c: New test.
> * gcc.target/riscv/sat_u_sub_imm-2_2.c: New test.
> * gcc.target/riscv/sat_u_sub_imm-3.c: New test.
> * gcc.target/riscv/sat_u_sub_imm-3_1.c: New test.
> * gcc.target/riscv/sat_u_sub_imm-3_2.c: New test.
> * gcc.target/riscv/sat_u_sub_imm-4.c: New test.
> * gcc.target/riscv/sat_u_sub_imm-run-1.c: New test.
> * gcc.target/riscv/sat_u_sub_imm-run-2.c: New test.
> * gcc.target/riscv/sat_u_sub_imm-run-3.c: New test.
> * gcc.target/riscv/sat_u_sub_imm-run-4.c: New test.
OK. I'm assuming we don't have to worry about the case where X is wider
than Xmode? ie, a DImode on rv32?
Jeff
