Re: [PATCH v2 0/2] RISC-V: Optimize RVV epilogue logic.

2022-11-15 Thread juzhe.zh...@rivai.ai
bject: [PATCH v2 0/2] RISC-V: Optimize RVV epilogue logic. Current epilogue will generate "addi sp,sp,0" redundant instruction. ``` csrrt0,vlenb sllit1,t0,1 add sp,sp,t1 addisp,sp,0 ld s0,24(sp) addisp,sp,32

[PATCH v2 0/2] RISC-V: Optimize RVV epilogue logic.

2022-11-15 Thread jiawei
Current epilogue will generate "addi sp,sp,0" redundant instruction. ``` csrrt0,vlenb sllit1,t0,1 add sp,sp,t1 addisp,sp,0 ld s0,24(sp) addisp,sp,32 jr ra ``` Optimize it by check if adjust equal to zero, remove