Re: [PATCH v2] MIPS: IPL is 8bit in Cause register if TARGET_MCU

在 2022/2/12 16:47, Maciej W. Rozycki 写道: On Fri, 11 Feb 2022, Jeff Law wrote: If MIPS MCU extension is enable, the IPL section in Cause register has been expand to 8bit instead of 6bit. gcc/ChangeLog: * config/mips/mips.cc (mips_expand_prologue): IPL is 8bit for MCU ASE. OK

Re: [PATCH v2] MIPS: IPL is 8bit in Cause register if TARGET_MCU

On Fri, 11 Feb 2022, Jeff Law wrote: > > If MIPS MCU extension is enable, the IPL section in Cause register > > has been expand to 8bit instead of 6bit. > > > > gcc/ChangeLog: > > > > * config/mips/mips.cc (mips_expand_prologue): > > IPL is 8bit for MCU ASE. > OK But this is still wr

Re: [PATCH v2] MIPS: IPL is 8bit in Cause register if TARGET_MCU

On 2/8/2022 8:18 PM, YunQiang Su wrote: If MIPS MCU extension is enable, the IPL section in Cause register has been expand to 8bit instead of 6bit. gcc/ChangeLog: * config/mips/mips.cc (mips_expand_prologue): IPL is 8bit for MCU ASE. OK jeff

[PATCH v2] MIPS: IPL is 8bit in Cause register if TARGET_MCU

If MIPS MCU extension is enable, the IPL section in Cause register has been expand to 8bit instead of 6bit. gcc/ChangeLog: * config/mips/mips.cc (mips_expand_prologue): IPL is 8bit for MCU ASE. --- gcc/config/mips/mips.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) d