On Fri, 11 Feb 2022, Jeff Law wrote: > > If MIPS MCU extension is enable, the IPL section in Cause register > > has been expand to 8bit instead of 6bit. > > > > gcc/ChangeLog: > > > > * config/mips/mips.cc (mips_expand_prologue): > > IPL is 8bit for MCU ASE. > OK
But this is still wrong AFAICT. The mask is applied to the CP0 Status register according to the comment, but the layout of the interrupt bit-field is different between the CP0 Status and the CP0 Cause registers, so you can't just extract it from one of the two registers and directly apply to the other. I would like to know how this code has been verified. Maciej
