subject:"\[PATCH v1 8\/8\] RISC\-V\: Add testcases for unsigned .SAT_SUB vector form 10"

Re: [PATCH v1 8/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 10

2024-06-19 Thread ??????

lgtm --Reply to Message-- On Wed, Jun 19, 2024 21:17 PM pan2.li

[PATCH v1 8/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 10

2024-06-19 Thread pan2 . li

From: Pan Li After the middle-end support the form 10 of unsigned SAT_SUB and the RISC-V backend implement the .SAT_SUB for vector mode, thus add more test case to cover that. Form 10: #define DEF_VEC_SAT_U_SUB_FMT_10(T) \ void __attribute__((noinline))