.
>
>
>
> Thanks.
>
>
>
>
>
> juzhe.zh...@rivai.ai
>
>
>
> *From:* Jeff Law <mailto:jeffreya...@gmail.com>
>
> *Date:* 2024-02-23 16:29
>
> *To:*
jeffreyalaw ; kito.cheng ; Li,
Pan2
Cc: gcc-patches ; Wang, Yanzhang
; Robin Dapp ; palmer
; vineetg ; Patrick O'Neill
; Edwin Lu
Subject: Re: Re: [PATCH v1] RISC-V: Introduce gcc option mrvv-vector-bits for
RVV
I personally think it's better to has VLS compile option and attrib
es; juzhe.zhong; yanzhang.wang
Subject: Re: [PATCH v1] RISC-V: Introduce gcc option mrvv-vector-bits for RVV
On 2/23/24 01:22, Kito Cheng wrote:
> I would prefer to only keep zvl and scalable or zvl only, since I
> don't see too much value in specifying a value which different from
&g
On 2/23/24 01:22, Kito Cheng wrote:
I would prefer to only keep zvl and scalable or zvl only, since I
don't see too much value in specifying a value which different from
zvl*b, that's a legacy option used before zvl*b option was introduced,
and the reason to add that is that could used for com
I would prefer to only keep zvl and scalable or zvl only, since I
don't see too much value in specifying a value which different from
zvl*b, that's a legacy option used before zvl*b option was introduced,
and the reason to add that is that could used for compatible with
clang/LLVM for riscv_rvv_vec
From: Pan Li
This patch would like to introduce one new gcc option for RVV. To
appoint the bits size of one RVV vector register. Valid arguments to
'-mrvv-vector-bits=' are:
* 64
* 128
* 256
* 512
* 1024
* 2048
* 4096
* 8192
* 16384
* 32768
* 65536
* scalable
* zvl
1. The scalable will be the d
