Hello,
On 10 Sep 11:51, Richard Henderson wrote:
> On 09/10/2013 11:25 AM, Kirill Yukhin wrote:
> > Is it ok now?
>
>
> Yes.
Thanks a lot!
Checked into main trunk: http://gcc.gnu.org/ml/gcc-cvs/2013-09/msg00354.html
--
Thanks, K
On 09/10/2013 05:57 AM, Kirill Yukhin wrote:
> + { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi_1, "__builtin_ia32_kandhi",
> IX86_BUILTIN_KAND16, UNKNOWN, (int) HI_FTYPE_HI_HI },
Alternately, why not use the standard CODE_FOR_andhi3 expander?
r~
On 09/10/2013 11:25 AM, Kirill Yukhin wrote:
> Hello,
> On 10 Sep 09:17, Richard Henderson wrote:
>> On 09/10/2013 05:57 AM, Kirill Yukhin wrote:
>>> + { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi_1, "__builtin_ia32_kandhi",
>>> IX86_BUILTIN_KAND16, UNKNOWN, (int) HI_FTYPE_HI_HI },
>>
>> Alternately
Hello,
On 10 Sep 09:17, Richard Henderson wrote:
> On 09/10/2013 05:57 AM, Kirill Yukhin wrote:
> > + { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi_1, "__builtin_ia32_kandhi",
> > IX86_BUILTIN_KAND16, UNKNOWN, (int) HI_FTYPE_HI_HI },
>
> Alternately, why not use the standard CODE_FOR_andhi3 expander
On 09/10/2013 05:57 AM, Kirill Yukhin wrote:
> Do you still think we need "*"?
No, I suppose that's fine.
r~
Hello Richard,
Thanks for inputs.
On 09 Sep 10:39, Richard Henderson wrote:
> gen_andhi_1 is not used, nor is it likely to be in the future, therefore this
> should still have "*".
We're using it in patch 6/8 when introducing plugins:
+ { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi_1, "__builtin_ia3
On 08/29/2013 04:59 AM, Kirill Yukhin wrote:
> @@ -7616,10 +7677,10 @@
>[(set_attr "type" "alu")
> (set_attr "mode" "SI")])
>
> -(define_insn "*andhi_1"
> - [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,Ya")
> - (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
Hello,
On 04 Sep 22:45, Kirill Yukhin wrote:
> Hello,
>
> PING.
PING.
--
Thanks, K
Hello,
On 29 Aug 15:59, Kirill Yukhin wrote:
> /* Define parameter passing and return registers. */
> @@ -4219,8 +4225,13 @@ ix86_conditional_register_usage (void)
>
>/* If AVX512F is disabled, squash the registers. */
>if (! TARGET_AVX512F)
> -for (i = FIRST_EXT_REX_SSE_REG; i < L
Hello,
PING.
--
Thanks, K
Hello,
> Testing in progress, is it ok for trunk if pass?
I forgot to add clobber to split of andn,
so testing fail. Fixed.
Updated patch in the bottom.
Testing:
1. Bootstrap pass.
2. make check shows no regressions.
3. Spec 2000 & 2006 build show no regressions both with and without -mavx5
Hello,
On 28 Aug 13:17, Richard Henderson wrote:
> Uh, no, you can't just add it when doing the split. You could be adding it in
> a place that the flags register is live. You must ALWAYS have the clobber on
> the whole pattern when gprs are possible.
I see now, thanks a lot for explanation!
>
On 08/28/2013 11:38 AM, Kirill Yukhin wrote:
>> When combine puts the AND and the NOT together, we don't know what registers
>> we
>> want the data in. If we do not supply the general register alternative, with
>> the clobber, then we will be FORCED to implement the operation in the mask
>> regis
Hello Richard,
On 28 Aug 10:55, Richard Henderson wrote:
> On 08/28/2013 10:45 AM, Kirill Yukhin wrote:
> > Hello Richard,
> >
> > On 27 Aug 13:07, Richard Henderson wrote:
> >> On 08/27/2013 11:11 AM, Kirill Yukhin wrote:
> > What happened to the bmi andn alternative we discussed?
> >>> BMI
On 08/28/2013 10:45 AM, Kirill Yukhin wrote:
> Hello Richard,
>
> On 27 Aug 13:07, Richard Henderson wrote:
>> On 08/27/2013 11:11 AM, Kirill Yukhin wrote:
> What happened to the bmi andn alternative we discussed?
>>> BMI only supported for 4- and 8- byte integers, while
>>> kandw - for HI/QI
Hello Richard,
On 27 Aug 13:07, Richard Henderson wrote:
> On 08/27/2013 11:11 AM, Kirill Yukhin wrote:
> >> > What happened to the bmi andn alternative we discussed?
> > BMI only supported for 4- and 8- byte integers, while
> > kandw - for HI/QI
> >
>
> We're talking about values in registers. I
On 08/27/2013 11:11 AM, Kirill Yukhin wrote:
>> > What happened to the bmi andn alternative we discussed?
> BMI only supported for 4- and 8- byte integers, while
> kandw - for HI/QI
>
We're talking about values in registers. Ignoring the high bits of the andn
result still produces the correct re
On 27 Aug 22:11, Kirill Yukhin wrote:
Hello, I've while pasting the patch I've accidentally put
extra brace.
Pls Ignore it
> +(define_insn "kxnor"
> + [(set (match_operand:SWI12 0 "register_operand" "=r,!k")
> + (not:SWI12
> + (xor:SWI12
> + (match_operand:SWI12 1 "register_opera
Hello Reichard,
On 26 Aug 09:37, Richard Henderson wrote:
> On 08/26/2013 09:13 AM, Kirill Yukhin wrote:
> > +(define_split
> > + [(set (match_operand:SWI12 0 "mask_reg_operand")
> > + (any_logic:SWI12 (match_operand:SWI12 1 "mask_reg_operand")
> > +(match_operand:SWI12 2 "m
On 08/26/2013 09:13 AM, Kirill Yukhin wrote:
> +(define_split
> + [(set (match_operand:SWI12 0 "mask_reg_operand")
> + (any_logic:SWI12 (match_operand:SWI12 1 "mask_reg_operand")
> + (match_operand:SWI12 2 "mask_reg_operand")))
> + (clobber (reg:CC FLAGS_REG))]
> + "TAR
On 22 Aug 08:49, Richard Henderson wrote:
Hello,
> You can always split away the clobber after reload, as we do for
> when add gets implemented with lea.
I've refactored the patch, making mask logic insn patterns non-unspec.
Unfortunately I was unable to use '*' in mask alternative, since it is
n
On 08/22/2013 02:35 AM, Kirill Yukhin wrote:
> Despite of generic OR, mask version of OR do not clobber FLAGS_REG.
> Of course, we may conservatively think that it is, but I believe
> this is not good idea.
I believe that having two different patterns is a worse idea.
You can always split away th
Hello Richard,
On 19 Aug 14:17, Richard Henderson wrote:
> On 08/14/2013 12:23 AM, Kirill Yukhin wrote:
> > + ;; For AVX512F mask support
> > + UNSPEC_KIOR
> > + UNSPEC_KXOR
> > + UNSPEC_KAND
> > + UNSPEC_KANDN
>
> I thought we determined that you didn't need these,
> that "*Yk" as a constra
On 08/14/2013 12:23 AM, Kirill Yukhin wrote:
> + ;; For AVX512F mask support
> + UNSPEC_KIOR
> + UNSPEC_KXOR
> + UNSPEC_KAND
> + UNSPEC_KANDN
I thought we determined that you didn't need these,
that "*Yk" as a constraint was sufficient.
> +(define_insn "kandn"
> +(define_insn "kand"
> +(defi
Hello,
Patch was rebased on top of trunk.
It is applicable on top of [1/8] (which was rebased on new trunk today).
Testing:
1. Bootstrap pass.
2. make check shows no regressions.
3. Spec 2000 & 2006 build show no regressions both with and without -mavx512f
option.
4. Spec 2000 &
Hello!
> You can't read from memory into a mask register in QImode.
> This will fail if the memory was the last byte of a page,
> and the following page is not mapped.
>
> I expected you to need the following patch, to help spill
> and fill QImode values, but I havn't found a test case that
> ac
BTW, you've a bug in your movqi pattern:
> diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
> index b4c9ac5..d8401b5 100644
> --- a/gcc/config/i386/i386.md
> +++ b/gcc/config/i386/i386.md
> @@ -2298,7 +2298,7 @@
> ;; partial register stall can be caused there. Then we use movzx.
>
On 07/31/2013 05:02 AM, Kirill Yukhin wrote:
>
> There's ICE (max. number of generated reload insns per insn is achieved (90)),
> when LRA tried to save mask register before call. This was caused by fact
> that split_reg function
> in lra-constraints.c allocates memory for saved reg in
> SECOND
Hello,
In this patch we add support for new mask register k0-k7. Changes are mostly
strightforward, but there are two problems. First we can't use k0 as mask in
vector instructions, so we have introduce two register classes. One for use in
vector instruction with "k" constraint - corresponding to k
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