On 6/3/25 5:24 PM, Vineet Gupta wrote:
So as of tip of tree, even w/o the patch we no longer see the pattern "beq
, 0, .L12 "
They are replaced with reg anyways, so the test won't even show issue, even w/o
the fix.
beq a1,a5,.L12
beq a6,t0,.L12
beq a7,t3,.L12
I thi
On 5/21/25 11:07, Jeff Law wrote:
> On 5/20/25 4:05 PM, Edwin Lu wrote:
>> The instruction scheduler appears to be speculatively hoisting vsetvl
>> insns outside of their basic block without checking for data
>> dependencies. This resulted in a situation where the following occurs
>>
>> vs
On 5/20/25 4:05 PM, Edwin Lu wrote:
The instruction scheduler appears to be speculatively hoisting vsetvl
insns outside of their basic block without checking for data
dependencies. This resulted in a situation where the following occurs
vsetvli a5,a1,e32,m1,tu,ma
vle32.v v2,
On 5/20/25 4:05 PM, Edwin Lu wrote:
The instruction scheduler appears to be speculatively hoisting vsetvl
insns outside of their basic block without checking for data
dependencies. This resulted in a situation where the following occurs
vsetvli a5,a1,e32,m1,tu,ma
vle32.v v2,
The instruction scheduler appears to be speculatively hoisting vsetvl
insns outside of their basic block without checking for data
dependencies. This resulted in a situation where the following occurs
vsetvli a5,a1,e32,m1,tu,ma
vle32.v v2,0(a0)
sub a1,a1,a5 <-- a1 poten
