Re: [PATCH 2/7] RISC-V: Add support for the XAndesperf ISA extension.

On 6/23/25 3:02 AM, KuanLin Chen wrote: Hi, This patch adds support for the XAndesperf ISA extension. The 32-bit AndeStar V5 extension includes branch instructions, load effective address instructions, and string processing instructions for performance improvement. New INSN patterns are added

[PATCH 2/7] RISC-V: Add support for the XAndesperf ISA extension.

Hi, This patch adds support for the XAndesperf ISA extension. The 32-bit AndeStar V5 extension includes branch instructions, load effective address instructions, and string processing instructions for performance improvement. New INSN patterns are added into the new file andes.md as a seprated ven

Re: [PATCH 2/7] RISC-V: Add support for the XAndesperf ISA extension.

> +++ b/gcc/config/riscv/andes.md > @@ -0,0 +1,430 @@ > +;; Machine description for Andes vendor extensions > +;; Copyright (C) 2021-2025 Free Software Foundation, Inc. 2025 rather than 2021-2025 >+(define_constraint "ads_Bz07" Could you rename it to Ou07? >+ "Zero extended immediate 7-bit v