Just a followup on this patch.
We did some run-time performance testing internally on this set of
change on sparc M8 machine with -mmisalign and -mno-misalign
based on the latest upstream gcc
for CPU2017 C/C++ SPEED run:
***without -O, -mmisalign slowdown the run-time performance about 4% on
av
> On Aug 3, 2017, at 11:40 AM, David Miller wrote:
>
> From: Qing Zhao
> Date: Thu, 3 Aug 2017 10:37:15 -0500
>
>> all the special handling on STRICT_ALIGNMENT or
>> SLOW_UNALIGNMENT_ACCESS in these codes have the following common
>> logic:
>>
>> if the memory access is known to be not-aligne
From: Qing Zhao
Date: Thu, 3 Aug 2017 10:37:15 -0500
> all the special handling on STRICT_ALIGNMENT or
> SLOW_UNALIGNMENT_ACCESS in these codes have the following common
> logic:
>
> if the memory access is known to be not-aligned well during
> compilation time, if the targeted platform does NOT
To be more specified, when reading all the codes corresponding to
“STRICT_ALIGNMENT” and “SLOW_UNALIGNMENT_ACCESS” in gcc
(NOTE, SLOW_UNALIGNMENT_ACCESS is the same as STRICT_ALIGNMENT when it is NOT
defined explicitly, this is the case for SPARC)
We can get the following summary:
all the spe
> On Aug 2, 2017, at 6:17 PM, David Miller wrote:
>
> From: Qing Zhao
> Date: Wed, 2 Aug 2017 14:41:51 -0500
>
>> so, could you please specify what kind of side effects will have
>> when set STRICT_ALIGNMENT to true on TARGET_MISALIGN?
>
> Why don't you read the code rather than just relying
From: Qing Zhao
Date: Wed, 2 Aug 2017 14:41:51 -0500
> so, could you please specify what kind of side effects will have
> when set STRICT_ALIGNMENT to true on TARGET_MISALIGN?
Why don't you read the code rather than just relying upon what
high level description is given by the documentation inst
Hi, David,
thanks a lot for your comment.
see my reply below
> STRICT_ALIGNMENT has a lot of implications.
from the definition of STRICT_ALIGNMENT:
/* Set this nonzero if move instructions will actually fail to work
when given unaligned data. */
#define STRICT_ALIGNMENT 1
for MISALIGN_TAR
From: qinzhao
Date: Wed, 2 Aug 2017 10:27:51 -0500
> This patch adds support to GCC for the misaligned load/store
> instructions introduced in the Oracle SPARC Architecture 2017 and
> implemented by the SPARC M8 processor.
>
> A new command line option -mmisaligned is added, tha
This patch adds support to GCC for the misaligned load/store
instructions introduced in the Oracle SPARC Architecture 2017 and
implemented by the SPARC M8 processor.
A new command line option -mmisaligned is added, that activates the
usage of the new instructions.
The SPAR
