Just a followup on this patch.

We did some run-time performance testing internally on this set of
change on sparc M8 machine with -mmisalign and -mno-misalign
based on the latest upstream gcc

for CPU2017 C/C++ SPEED run:

***without -O,  -mmisalign slowdown the run-time performance about 4% on
average

This is mainly due to the following workaround to misaligned support in
M8: (config/sparc/sparc.c)

+/* for misaligned ld/st provided by M8, the IMM field is 10-bit wide
+   other than the 13-bit for regular ld/st.
+   The best solution for this problem is to distinguish each ld/st
+   whether it's aligned or misaligned. However, due to the current
+   design of the common routine TARGET_LEGITIMATE_ADDRESS_P,  only
+   the ADDR of a ld/st is passed to the routine, the align info
+   carried by the corresponding MEM is NOT passed in. without changing
+   the prototype of TARGET_LEGITIMATE_ADDRESS_P, we cannot use this
+   best solution.
+   as a workaround, we have to conservatively treat ALL IMM field of
+   a ld/st insn on a MISALIGNED target is 10-bit wide.
+   the side-effect of this workaround is:  there will be additiona
+   REG<-IMM insn generated for regular ld/st when -mmisalign is ON.
+   However, such additional reload insns should be very easily to be
+   removed by a set of optimization whenever -O specified.
+*/
+#define RTX_OK_FOR_OFFSET_P(X, MODE)                     \
+  (CONST_INT_P (X)                                       \
+   && ((!TARGET_MISALIGN                                 \
+        && INTVAL (X) >=3D3D -0x1000                         \
+        && INTVAL (X) <=3D3D (0x1000 - GET_MODE_SIZE (MODE)))\
+    || (TARGET_MISALIGN                                  \
+        && INTVAL (X) >=3D3D -0x0400                         \
+        && INTVAL (X) <=3D3D (0x0400 - GET_MODE_SIZE (MODE)))))

due to this run-time regression introduced by this workaround is not
trivial, We decided to hold on this
set of change at this time.

Thanks.

Qing

> 
> This set of change is to provide a way to use misaligned load/store insns to 
> implement the compiler-time known unaligned memory access,  -mno-misalign can 
> be used
> to disable such behavior very easily if our performance data shows that 
> misaligned load/store insns are slower than the current software emulation. 
> 
> Qing

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