Re: [PATCH] x86: Require MMX for __builtin_ia32_maskmovq

2020-11-01 Thread Uros Bizjak via Gcc-patches
> Since "MASKMOVQ mm1, mm2" is an SSE instruction which requires MMX and > MMX/SSE ISAs are handled separately, make __builtin_ia32_maskmovq require > MMX instead of SSE. > > gcc/ > > PR target/97140 > * config/i386/i386-expand.c (ix86_expand_builtin): Require MMX > for __builtin_ia32_maskmovq. > >

PING^2 [PATCH] x86: Require MMX for __builtin_ia32_maskmovq

2020-10-31 Thread H.J. Lu via Gcc-patches
On Fri, Oct 2, 2020 at 6:28 AM H.J. Lu wrote: > > On Mon, Sep 21, 2020 at 6:09 AM H.J. Lu wrote: > > > > On Mon, Sep 21, 2020 at 5:54 AM H.J. Lu wrote: > > > > > > Since "MASKMOVQ mm1, mm2" is an SSE instruction which requires MMX and > > > MMX/SSE ISAs are handled separately, make __builtin_ia3

PING [PATCH] x86: Require MMX for __builtin_ia32_maskmovq

2020-10-02 Thread H.J. Lu via Gcc-patches
On Mon, Sep 21, 2020 at 6:09 AM H.J. Lu wrote: > > On Mon, Sep 21, 2020 at 5:54 AM H.J. Lu wrote: > > > > Since "MASKMOVQ mm1, mm2" is an SSE instruction which requires MMX and > > MMX/SSE ISAs are handled separately, make __builtin_ia32_maskmovq require > > MMX instead of SSE. > > > > gcc/ > > >

Re: [PATCH] x86: Require MMX for __builtin_ia32_maskmovq

2020-09-21 Thread H.J. Lu via Gcc-patches
operand" "y") > (mem:V8QI (match_dup 0))] > UNSPEC_MASKMOV))] > - "TARGET_SSE || TARGET_3DNOW_A" > + "TARGET_MMX || TARGET_3DNOW_A" >;; @@@ check ordering of operands in intel/nonintel syntax >"

[PATCH] x86: Require MMX for __builtin_ia32_maskmovq

2020-09-21 Thread H.J. Lu via Gcc-patches
Since "MASKMOVQ mm1, mm2" is an SSE instruction which requires MMX and MMX/SSE ISAs are handled separately, make __builtin_ia32_maskmovq require MMX instead of SSE. gcc/ PR target/97140 * config/i386/i386-expand.c (ix86_expand_builtin): Require MMX for __builtin_ia32_maskm