Re: [PATCH] loop-iv, riscv: Fix get_biv_step_1 for RISC-V [PR117506]

On 2/5/25 10:57 AM, Jakub Jelinek wrote: Hi! The following test ICEs on RISC-V at least latently since r14-1622-g99bfdb072e67fa3fe294d86b4b2a9f686f8d9705 which added RISC-V specific case to get_biv_step_1 to recognize also ({zero,sign}_extend:DI (plus:SI op0 op1)) The reason for the ICE is t

Re: [PATCH] loop-iv, riscv: Fix get_biv_step_1 for RISC-V [PR117506]

On 2/5/25 11:11 AM, Palmer Dabbelt wrote: On Wed, 05 Feb 2025 09:57:56 PST (-0800), ja...@redhat.com wrote: Hi! The following test ICEs on RISC-V at least latently since r14-1622-g99bfdb072e67fa3fe294d86b4b2a9f686f8d9705 which added RISC-V specific case to get_biv_step_1 to recognize also ({

Re: [PATCH] loop-iv, riscv: Fix get_biv_step_1 for RISC-V [PR117506]

> Hi! > > The following test ICEs on RISC-V at least latently since > r14-1622-g99bfdb072e67fa3fe294d86b4b2a9f686f8d9705 which added > RISC-V specific case to get_biv_step_1 to recognize also > ({zero,sign}_extend:DI (plus:SI op0 op1)) > > The reason for the ICE is that op1 in this case is CONST_PO

Re: [PATCH] loop-iv, riscv: Fix get_biv_step_1 for RISC-V [PR117506]

On Wed, Feb 05, 2025 at 10:11:27AM -0800, Palmer Dabbelt wrote: > Jeff would know way better than I do here, but I think this is just trying > to match addiw-type patterns and thus CONST_INT would be OK because we only > have 12-bit constants here. The code looks at REG_EQUIV/REG_EQUAL notes, so i

Re: [PATCH] loop-iv, riscv: Fix get_biv_step_1 for RISC-V [PR117506]

On Wed, 05 Feb 2025 09:57:56 PST (-0800), ja...@redhat.com wrote: Hi! The following test ICEs on RISC-V at least latently since r14-1622-g99bfdb072e67fa3fe294d86b4b2a9f686f8d9705 which added RISC-V specific case to get_biv_step_1 to recognize also ({zero,sign}_extend:DI (plus:SI op0 op1)) The r

[PATCH] loop-iv, riscv: Fix get_biv_step_1 for RISC-V [PR117506]

Hi! The following test ICEs on RISC-V at least latently since r14-1622-g99bfdb072e67fa3fe294d86b4b2a9f686f8d9705 which added RISC-V specific case to get_biv_step_1 to recognize also ({zero,sign}_extend:DI (plus:SI op0 op1)) The reason for the ICE is that op1 in this case is CONST_POLY_INT which u