> Hi!
>
> The following test ICEs on RISC-V at least latently since
> r14-1622-g99bfdb072e67fa3fe294d86b4b2a9f686f8d9705 which added
> RISC-V specific case to get_biv_step_1 to recognize also
> ({zero,sign}_extend:DI (plus:SI op0 op1))
>
> The reason for the ICE is that op1 in this case is CONST_POLY_INT
> which unlike the really expected VOIDmode CONST_INTs has its own
> mode and still satisfies CONSTANT_P.
> GET_MODE (rhs) (SImode) is different from outer_mode (DImode), so
> the function later does
> *inner_step = simplify_gen_binary (code, outer_mode,
> *inner_step, op1);
> but that obviously ICEs because while *inner_step is either VOIDmode
> or DImode, op1 has SImode.
Ah, we had this before but it indeed went latent:
https://gcc.gnu.org/pipermail/gcc-patches/2024-February/645059.html
Yours seems the better solution.
--
Regards
Robin
