Committed, thanks Robin.
Pan
-Original Message-
From: Robin Dapp
Sent: Friday, November 10, 2023 4:12 PM
To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org
Cc: rdapp@gmail.com; kito.ch...@gmail.com; kito.ch...@sifive.com;
jeffreya...@gmail.com
Subject: Re: [PATCH] RISC-V: Robustify
Hi Juzhe,
yes, that's reasonable. OK.
Regards
Robin
Although current GCC didn't cause ICE when I create FP16 vec_init case
with -march=rv64gcv (no ZVFH), current vec_init pattern looks wrong.
Since V_VLS FP16 predicate is TARGET_VECTOR_ELEN_FP_16, wheras vec_init
needs vfslide1down/vfslide1up.
It makes more sense to robustify the vec_init patterns
