Re: [PATCH] RISC-V: Fix th.extu operands exceeding range on rv32.

2024-09-18 Thread Jeff Law
On 9/17/24 2:57 AM, Xianmiao Qu wrote: The Combine Pass may generate zero_extract instructions that are out of range. Drawing from other architectures like AArch64, we should impose restrictions on the "*th_extu4" pattern. gcc/ * config/riscv/thead.md (*th_extu4): Fix th.extu

[PATCH] RISC-V: Fix th.extu operands exceeding range on rv32.

2024-09-17 Thread Xianmiao Qu
The Combine Pass may generate zero_extract instructions that are out of range. Drawing from other architectures like AArch64, we should impose restrictions on the "*th_extu4" pattern. gcc/ * config/riscv/thead.md (*th_extu4): Fix th.extu operands exceeding range on rv32. *