RE: [PATCH] RISC-V: Add testcases for unsigned imm vec SAT_SUB form2~4

2025-04-25 Thread Li, Pan2
PM To: xuli1 mailto:xu...@eswincomputing.com>>; gcc-patches mailto:gcc-patches@gcc.gnu.org>> Cc: kito.cheng mailto:kito.ch...@gmail.com>>; palmer mailto:pal...@dabbelt.com>>; Li, Pan2 mailto:pan2...@intel.com>>; xuli1 mailto:xu...@eswincomputing.com>&g

Re: [PATCH] RISC-V: Add testcases for unsigned imm vec SAT_SUB form2~4

2025-01-02 Thread 钟居哲
LGTM. juzhe.zh...@rivai.ai From: Li Xu Date: 2025-01-02 16:02 To: gcc-patches CC: kito.cheng; palmer; juzhe.zhong; pan2.li; xuli Subject: [PATCH] RISC-V: Add testcases for unsigned imm vec SAT_SUB form2~4 From: xuli Form2: void __attribute__((noinline)) \ vec_sat_u_sub_imm##IMM

[PATCH] RISC-V: Add testcases for unsigned imm vec SAT_SUB form2~4

2025-01-02 Thread Li Xu
From: xuli Form2: void __attribute__((noinline)) \ vec_sat_u_sub_imm##IMM##_##T##_fmt_2 (T *out, T *in, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \