subject:"\[PATCH\] RISC\-V\: Add TAREGT_VECTOR check into VLS modes"

RE: [PATCH] RISC-V: Add TAREGT_VECTOR check into VLS modes

2023-08-11 Thread Li, Pan2 via Gcc-patches

: Add TAREGT_VECTOR check into VLS modes On 8/11/23 20:30, Juzhe-Zhong wrote: > This patch fixes bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110994 > > This is caused VLS modes incorrect codes int register allocation. > > The original case trigger the ICE is fortran code but

Re: [PATCH] RISC-V: Add TAREGT_VECTOR check into VLS modes

2023-08-11 Thread Jeff Law via Gcc-patches

On 8/11/23 20:30, Juzhe-Zhong wrote: This patch fixes bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110994 This is caused VLS modes incorrect codes int register allocation. The original case trigger the ICE is fortran code but I can reproduce with a C code. PR target/110994 gc

[PATCH] RISC-V: Add TAREGT_VECTOR check into VLS modes

2023-08-11 Thread Juzhe-Zhong

This patch fixes bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110994 This is caused VLS modes incorrect codes int register allocation. The original case trigger the ICE is fortran code but I can reproduce with a C code. PR target/110994 gcc/ChangeLog: * config/riscv/riscv-