Committed, thanks Jeff. Pan
-----Original Message----- From: Gcc-patches <gcc-patches-bounces+pan2.li=intel....@gcc.gnu.org> On Behalf Of Jeff Law via Gcc-patches Sent: Saturday, August 12, 2023 11:57 AM To: Juzhe-Zhong <juzhe.zh...@rivai.ai>; gcc-patches@gcc.gnu.org Cc: kito.ch...@sifive.com; kito.ch...@gmail.com; rdapp....@gmail.com Subject: Re: [PATCH] RISC-V: Add TAREGT_VECTOR check into VLS modes On 8/11/23 20:30, Juzhe-Zhong wrote: > This patch fixes bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110994 > > This is caused VLS modes incorrect codes int register allocation. > > The original case trigger the ICE is fortran code but I can reproduce > with a C code. > > PR target/110994 > > gcc/ChangeLog: > > * config/riscv/riscv-opts.h (TARGET_VECTOR_VLS): Add TARGET_VETOR. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/autovec/vls/pr110994.c: New test. OK jeff
