Re: [PATCH] Check suitability of spill register for mode

On 11/14/19 7:34 AM, Kwok Cheung Yeung wrote: Hello Currently, when choosing a spill register, GCC just picks the first available register in the register class returned by the TAQRGET_SPILL_CLASS hook that doesn't conflict. On AMD GCN this can cause problems as DImode values stored in SGPRs

[PATCH] Check suitability of spill register for mode

Hello Currently, when choosing a spill register, GCC just picks the first available register in the register class returned by the TAQRGET_SPILL_CLASS hook that doesn't conflict. On AMD GCN this can cause problems as DImode values stored in SGPRs must start on an even register number and TIm