> About the 1st question. Before gcc4.7, the only class (allocno class)
> used for coloring can be a cover class. So it was not possible to use
> GENERAL_OR_EXTRA_FP_REGS in gcc4.6 and older versions. Starting gcc4.7,
> class used for coloring can be any class which is more profitable than
> mem
On 09/28/2011 06:38 PM, Eric Botcazou wrote:
[Vlad, if you have a few minutes, would you mind having a look at the couple of
questions at the end of the message? Thanks in advance].
No problem.
Here are the results of the investigation. Pseudo 116 needs to be assigned a
hard register. It is
From: Eric Botcazou
Date: Thu, 29 Sep 2011 00:38:49 +0200
> [Vlad, if you have a few minutes, would you mind having a look at the couple
> of
> questions at the end of the message? Thanks in advance].
Vlad, ping?
[Vlad, if you have a few minutes, would you mind having a look at the couple of
questions at the end of the message? Thanks in advance].
> No problem.
Here are the results of the investigation. Pseudo 116 needs to be assigned a
hard register. It is used mostly in vector instructions so we wo
From: Eric Botcazou
Date: Tue, 27 Sep 2011 10:04:35 +0200
> Yes, I noticed it, but this is a regression and probably is
> unrelated to the vectorizer. IIRC the problem comes from the RA,
> which forces a bogus reload. That wouldn't be the first time some
> RA change breaks vector support on SPA
> Eric, I'm sure you have noticed this, but the Sparc target test
> "combined-1.c" fails for some time on 32-bit because of how float
> arguments are passed in the 32-bit SPARC ABI.
>
> Since they are passed in integer registers, the vectorizer does
> the initial logical operations using non-VIS in
Eric, I'm sure you have noticed this, but the Sparc target test
"combined-1.c" fails for some time on 32-bit because of how float
arguments are passed in the 32-bit SPARC ABI.
Since they are passed in integer registers, the vectorizer does
the initial logical operations using non-VIS instructions
