[Vlad, if you have a few minutes, would you mind having a look at the couple of
questions at the end of the message? Thanks in advance].
> No problem.
Here are the results of the investigation. Pseudo 116 needs to be assigned a
hard register. It is used mostly in vector instructions so we would like it
to be assigned a FP reg, but it is initialized in insn 2:
(insn 2 5 3 2 (set (reg/v:V4HI 116 [ a ])
(reg:V4HI 24 %i0 [ a ])) combined-1.c:7 93 {*movdf_insn_sp32_v9}
(expr_list:REG_DEAD (reg:V4HI 24 %i0 [ a ])
(nil)))
so it ends up being assigned the (integer) argument register %i0 instead. It
used to be assigned a FP reg as expected with the GCC 4.6.x series.
The register class preference discovery is OK:
r116: preferred EXTRA_FP_REGS, alternative GENERAL_OR_EXTRA_FP_REGS,
allocno GENERAL_OR_EXTRA_FP_REGS
a2 (r116,l0) best EXTRA_FP_REGS, allocno GENERAL_OR_EXTRA_FP_REGS
i.e. EXTRA_FP_REGS is "preferred"/"best". Then it seems that this preference
is dropped and only the class of the allocno, GENERAL_OR_EXTRA_FP_REGS, is
handed down to the coloring stage. By contrast, in the GCC 4.6 series, the
cover_class of the allocno is EXTRA_FP_REGS.
The initial cost for %i0 is twice as high (24000) as the cost of FP regs. But
then it is reduced by 12000 when process_bb_node_for_hard_reg_moves sees insn
2 above and then again by 12000 when process_regs_for_copy sees the same insn.
So, in the end, %i0 is given cost 0 and thus beats every other register. This
doesn't happen in the GCC 4.6 series because %i0 isn't in the cover_class.
This is at -O1. At -O2, there is an extra pass at the discovery stage and it
sets the class of the allocno to EXTRA_FP_REGS, like with the GCC 4.6 series,
so a simple workaround is
Index: gcc.target/sparc/combined-1.c
===================================================================
--- gcc.target/sparc/combined-1.c (revision 179316)
+++ gcc.target/sparc/combined-1.c (working copy)
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+/* { dg-options "-O2 -mcpu=ultrasparc -mvis" } */
typedef short vec16 __attribute__((vector_size(8)));
typedef int vec32 __attribute__((vector_size(8)));
Finally the couple of questions:
1. Is it expected that the register class preference be dropped at -O1?
2. Is it expected that a single insn be processed by 2 different mechanisms
that independently halve the initial cost of a hard register?
--
Eric Botcazou
