hours to object before pushing it.
Thanks,
James
> From: Wilco Dijkstra
> Sent: 25 October 2016 18:08
> To: GCC Patches
> Cc: nd
> Subject: [PATCH][AArch64] Improve SHA1 scheduling
>
> SHA1H instructions may be scheduled after a SHA1C instruction
> that uses the sa
Wilco Dijkstra wrote:
> James Greenhalgh wrote:
>
> > I haven't seen a follow-up to Andrew's point regarding other
> > read-modify-write operations.
> >
> > Did youi investigate the cost of these?
>
> I looked at whether there are other similar cases, but it appears SHA1
> is unique due to the odd
James Greenhalgh wrote:
> I haven't seen a follow-up to Andrew's point regarding other
> read-modify-write operations.
>
> Did youi investigate the cost of these?
I looked at whether there are other similar cases, but it appears SHA1
is unique due to the odd dataflow, the mismatch in latencies a
er 2016 18:08
> To: GCC Patches
> Cc: nd
> Subject: [PATCH][AArch64] Improve SHA1 scheduling
>
> SHA1H instructions may be scheduled after a SHA1C instruction
> that uses the same input register. However SHA1C updates its input,
> so if SHA1H is scheduled after it, it requ
ping
From: Wilco Dijkstra
Sent: 25 October 2016 18:08
To: GCC Patches
Cc: nd
Subject: [PATCH][AArch64] Improve SHA1 scheduling
SHA1H instructions may be scheduled after a SHA1C instruction
that uses the same input register. However SHA1C updates its input,
so if SHA1H is scheduled
ping
From: Wilco Dijkstra
Sent: 25 October 2016 18:08
To: GCC Patches
Cc: nd
Subject: [PATCH][AArch64] Improve SHA1 scheduling
SHA1H instructions may be scheduled after a SHA1C instruction
that uses the same input register. However SHA1C updates its input,
so if SHA1H is scheduled after
Andrew Pinski wrote:
> On Tue, Oct 25, 2016 at 10:08 AM, Wilco Dijkstra
> wrote:
> > SHA1H instructions may be scheduled after a SHA1C instruction
> > that uses the same input register. However SHA1C updates its input,
> > so if SHA1H is scheduled after it, it requires an extra move.
> > Increas
On Tue, Oct 25, 2016 at 10:08 AM, Wilco Dijkstra wrote:
> SHA1H instructions may be scheduled after a SHA1C instruction
> that uses the same input register. However SHA1C updates its input,
> so if SHA1H is scheduled after it, it requires an extra move.
> Increase the priority of SHA1H to ensure
ping
From: Wilco Dijkstra
Sent: 25 October 2016 18:08
To: GCC Patches
Cc: nd
Subject: [PATCH][AArch64] Improve SHA1 scheduling
SHA1H instructions may be scheduled after a SHA1C instruction
that uses the same input register. However SHA1C updates its input,
so if SHA1H is scheduled after
SHA1H instructions may be scheduled after a SHA1C instruction
that uses the same input register. However SHA1C updates its input,
so if SHA1H is scheduled after it, it requires an extra move.
Increase the priority of SHA1H to ensure it gets scheduled
earlier, avoiding the move.
Is this something
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