Re: [PATCH, ARM] Fix unrecognizable vector comparisons

2013-08-08 Thread Ramana Radhakrishnan
On 08/01/13 03:04, Zhenqiang Chen wrote: Thank you all for the comments. The patch is updated as: 1) Revert it to the original one. 2) For the testcase, replace the dg-options with /* { dg-do compile } */ /* { dg-require-effective-target arm_neon } */ /* { dg-add-options arm_neon } */ /* { dg-opt

[Ping] Re: [PATCH, ARM] Fix unrecognizable vector comparisons

2013-08-08 Thread Zhenqiang Chen
Ping? Is it OK for 4.8 and trunk? Thanks! -Zhenqiang On 1 August 2013 10:04, Zhenqiang Chen wrote: > Thank you all for the comments. The patch is updated as: > 1) Revert it to the original one. > 2) For the testcase, replace the dg-options with > /* { dg-do compile } */ > /* { dg-require-effecti

Re: [PATCH, ARM] Fix unrecognizable vector comparisons

2013-07-31 Thread Zhenqiang Chen
Thank you all for the comments. The patch is updated as: 1) Revert it to the original one. 2) For the testcase, replace the dg-options with /* { dg-do compile } */ /* { dg-require-effective-target arm_neon } */ /* { dg-add-options arm_neon } */ /* { dg-options "-O3" } */ Bootstrap on Chromebook an

Re: [PATCH, ARM] Fix unrecognizable vector comparisons

2013-07-08 Thread Jakub Jelinek
On Mon, Jul 08, 2013 at 11:44:04AM -0700, Janis Johnson wrote: > >> @@ -0,0 +1,16 @@ > >> +/* { dg-do compile } */ > >> +/* { dg-options "-O3 -mfpu=neon -mcpu=cortex-a9 -mthumb > >> -mfloat-abi=hard -S" } */ > >> > >> dg-add-options arm_neon ? > >> dg-require-effective-target arm_neon ? > > > > I

Re: [PATCH, ARM] Fix unrecognizable vector comparisons

2013-07-08 Thread Janis Johnson
On 07/08/2013 08:32 AM, Zhenqiang Chen wrote: > On 8 July 2013 20:57, Ramana Radhakrishnan wrote: >> Not yet. Why is this not a problem in the LT / UNLT case ? > >>From the context, after the first switch, only GE/LE/EQ might have > operands[5] which is not REG (CONST0_RTX). For others including

Re: [PATCH, ARM] Fix unrecognizable vector comparisons

2013-07-08 Thread James Greenhalgh
On Mon, Jul 08, 2013 at 04:32:13PM +0100, Zhenqiang Chen wrote: > On 8 July 2013 20:57, Ramana Radhakrishnan wrote: > > Not yet. Why is this not a problem in the LT / UNLT case ? > > From the context, after the first switch, only GE/LE/EQ might have > operands[5] which is not REG (CONST0_RTX). Fo

Re: [PATCH, ARM] Fix unrecognizable vector comparisons

2013-07-08 Thread Zhenqiang Chen
On 8 July 2013 20:57, Ramana Radhakrishnan wrote: > Not yet. Why is this not a problem in the LT / UNLT case ? >From the context, after the first switch, only GE/LE/EQ might have operands[5] which is not REG (CONST0_RTX). For others including LT/UNLT, operands[5] should be REG. if (!REG_P (opera

Re: [PATCH, ARM] Fix unrecognizable vector comparisons

2013-07-08 Thread Ramana Radhakrishnan
Not yet. Why is this not a problem in the LT / UNLT case ? The testcase is not correctly written. @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mfpu=neon -mcpu=cortex-a9 -mthumb -mfloat-abi=hard -S" } */ dg-add-options arm_neon ? dg-require-effective-target arm_neon ? reg

Re: [PATCH, ARM] Fix unrecognizable vector comparisons

2013-06-26 Thread Zhenqiang Chen
On 18 June 2013 17:41, Ramana Radhakrishnan wrote: > On 06/18/13 09:50, Zhenqiang Chen wrote: >> >> Hi, >> >> During expand, function vcond inverses some CMP, e.g. >> >> a LE b -> b GE a >> >> But if "b" is "CONST0_RTX", "b GE a" will be an illegal insn. >> >> (insn 933 932 934 113 (set (reg:V

Re: [PATCH, ARM] Fix unrecognizable vector comparisons

2013-06-18 Thread Ramana Radhakrishnan
On 06/18/13 09:50, Zhenqiang Chen wrote: Hi, During expand, function vcond inverses some CMP, e.g. a LE b -> b GE a But if "b" is "CONST0_RTX", "b GE a" will be an illegal insn. (insn 933 932 934 113 (set (reg:V4SI 1027) (unspec:V4SI [ (const_vector:V4SI [

[PATCH, ARM] Fix unrecognizable vector comparisons

2013-06-18 Thread Zhenqiang Chen
Hi, During expand, function vcond inverses some CMP, e.g. a LE b -> b GE a But if "b" is "CONST0_RTX", "b GE a" will be an illegal insn. (insn 933 932 934 113 (set (reg:V4SI 1027) (unspec:V4SI [ (const_vector:V4SI [ (const_int 0 [0])