Re: [PATCH, AArch64] atomics: prefetch the destination for write prior to ldxr/stxr loops

2016-05-27 Thread James Greenhalgh
On Tue, Mar 15, 2016 at 03:31:30PM +, James Greenhalgh wrote: > On Mon, Mar 07, 2016 at 10:54:25PM -0800, Andrew Pinski wrote: > > On Mon, Mar 7, 2016 at 8:12 PM, Yangfei (Felix) > > wrote: > > >> On Mon, Mar 7, 2016 at 7:27 PM, Yangfei (Felix) > > >> wrote: > > >> > Hi, > > >> > > > >> >

Re: [PATCH, AArch64] atomics: prefetch the destination for write prior to ldxr/stxr loops

2016-03-15 Thread James Greenhalgh
On Mon, Mar 07, 2016 at 10:54:25PM -0800, Andrew Pinski wrote: > On Mon, Mar 7, 2016 at 8:12 PM, Yangfei (Felix) wrote: > >> On Mon, Mar 7, 2016 at 7:27 PM, Yangfei (Felix) > >> wrote: > >> > Hi, > >> > > >> > As discussed in LKML: > >> http://lists.infradead.org/pipermail/linux-arm-kernel/2

Re: [PATCH, AArch64] atomics: prefetch the destination for write prior to ldxr/stxr loops

2016-03-07 Thread Andrew Pinski
On Mon, Mar 7, 2016 at 8:12 PM, Yangfei (Felix) wrote: >> On Mon, Mar 7, 2016 at 7:27 PM, Yangfei (Felix) >> wrote: >> > Hi, >> > >> > As discussed in LKML: >> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/355996.html, >> the >> cost of changing a cache line >> > from

Re: [PATCH, AArch64] atomics: prefetch the destination for write prior to ldxr/stxr loops

2016-03-07 Thread Yangfei (Felix)
> On Mon, Mar 7, 2016 at 7:27 PM, Yangfei (Felix) wrote: > > Hi, > > > > As discussed in LKML: > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/355996.html, > the > cost of changing a cache line > > from shared to exclusive state can be significant on aarch64 cores, > esp

Re: [PATCH, AArch64] atomics: prefetch the destination for write prior to ldxr/stxr loops

2016-03-07 Thread Andrew Pinski
On Mon, Mar 7, 2016 at 7:27 PM, Yangfei (Felix) wrote: > Hi, > > As discussed in LKML: > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/355996.html, > the cost of changing a cache line > from shared to exclusive state can be significant on aarch64 cores, > especially wh

[PATCH, AArch64] atomics: prefetch the destination for write prior to ldxr/stxr loops

2016-03-07 Thread Yangfei (Felix)
Hi, As discussed in LKML: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/355996.html, the cost of changing a cache line from shared to exclusive state can be significant on aarch64 cores, especially when this is triggered by an exclusive store, since it may result i