[PATCH, AArch64] atomics: prefetch the destination for write prior to ldxr/stxr loops

Mon, 07 Mar 2016 19:28:24 -0800 

Hi,

    As discussed in LKML: 
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/355996.html, 
the cost of changing a cache line
    from shared to exclusive state can be significant on aarch64 cores, 
especially when this is triggered by an exclusive store, since it may
    result in having to retry the transaction. 
    This patch makes use of the "prfm PSTL1STRM" instruction to prefetch cache 
lines for write prior to ldxr/stxr loops generated by the ll/sc atomic 
routines. 
    Bootstrapped on AArch64 server, is it OK? 

Thanks,
Felix

Attachment: aarch64-atomics-v0.diff
Description: aarch64-atomics-v0.diff

Reply via email to