On Mon, Jul 08, 2019 at 04:41:06PM +0100, Joel Hutton wrote:
> On 01/07/2019 18:03, James Greenhalgh wrote:
>
> >> gcc/testsuite/ChangeLog:
> >>
> >> 2019-06-12 Joel Hutton
> >>
> >> * gcc.target/aarch64/fmul_scvtf_1.c: New test.
> > This testcase will fail on ILP32 targets where unsi
On 01/07/2019 18:03, James Greenhalgh wrote:
>> gcc/testsuite/ChangeLog:
>>
>> 2019-06-12 Joel Hutton
>>
>> * gcc.target/aarch64/fmul_scvtf_1.c: New test.
> This testcase will fail on ILP32 targets where unsigned long will still
> live in a 'w' register.
Updated to use long long and u
On Wed, Jun 26, 2019 at 10:35:00AM +0100, Joel Hutton wrote:
> Ping, plus minor rework (mostly non-functional changes)
>
> gcc/ChangeLog:
>
> 2019-06-12 Joel Hutton
>
> * config/aarch64/aarch64-protos.h (aarch64_fpconst_pow2_recip): New
> prototype
> * config/aarch64/aarch6
Hi Joel,
This looks good. One more thing, the patterns need to be conditional
on check flag_trapping_math since the division can underflow and
reassociating it would remove that. Other than that I think this is ready,
but I can't approve.
Wilco
Ping, plus minor rework (mostly non-functional changes)
gcc/ChangeLog:
2019-06-12 Joel Hutton
* config/aarch64/aarch64-protos.h (aarch64_fpconst_pow2_recip): New
prototype
* config/aarch64/aarch64.c (aarch64_fpconst_pow2_recip): New function
* config/aarch64/aarch6
On 18/06/2019 11:37, Richard Earnshaw (lists) wrote:
> Start sentences with a capital letter. End them with a full stop.
> "inequal" isn't a word: you probably mean "unequal".
I've fixed this, the iterator is, however defined as 'fcvt_iesize'
and described in the adjacent comment in iterators.md
Wilco Dijkstra writes:
> > +/* If X is a positive CONST_DOUBLE with a value that is the reciprocal of
> a
> > + power of 2 (i.e 1/2^n) return the number of float bits. e.g. for
> x==(1/2^n)
> > + return n. Otherwise return -1. */
> > +int
> > +aarch64_fpconst_pow2_recip (rtx x)
> > +{
Hi,
And a few more comments:
> +/* If X is a positive CONST_DOUBLE with a value that is the reciprocal of a
> + power of 2 (i.e 1/2^n) return the number of float bits. e.g. for
> x==(1/2^n)
> + return n. Otherwise return -1. */
> +int
> +aarch64_fpconst_pow2_recip (rtx x)
> +{
> +
On 18/06/2019 10:11, Joel Hutton wrote:
> Hi,
>
> On 13/06/2019 18:26, Wilco Dijkstra wrote:
>> Wouldn't it be easier to just do exact_log2 (real_to_integer (&r0))
>> and then check the range is in 1..31?
> I've revised this section.
>> --- a/gcc/config/aarch64/aarch64.md
>> +++ b/gcc/config/aarch
Hi,
On 13/06/2019 18:26, Wilco Dijkstra wrote:
> Wouldn't it be easier to just do exact_log2 (real_to_integer (&r0))
> and then check the range is in 1..31?
I've revised this section.
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -6016,6 +6016,40 @@
> [(set_a
Hi Joel,
A few comments below:
+/* If X is a positive CONST_DOUBLE with a value that is the reciprocal of a
+ power of 2 (i.e 1/2^n) return the number of float bits. e.g. for x==(1/2^n)
+ return log2 (n). Otherwise return 0. */
+int
+aarch64_fpconst_pow2_recip (rtx x)
+{
+ REAL_VALUE_TYPE r
Hi all,
There was previously no backend pattern to utilise the scvtf fbits option.
Where a fixed point is converted to a float, and divided by a power of 2, (or
multiplied by the reciprocal of a power of 2), this can be combined into a
single scvtf with fbits operation. This patch adds a patter
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