[PATCH] [RISC-V]Support -mcpu for Xuantie cpu

gcc/ChangeLog: * config/riscv/riscv-cores.def (RISCV_TUNE): Add xt-c908, xt-c908v, xt-c910, xt-c910v2, xt-c920, xt-c920v2. (RISCV_CORE): Add xt-c908, xt-c908v, xt-c910, xt-c910v2, xt-c920, xt-c920v2 * config/riscv/riscv.cc: Add xt-c908, xt-c908v, xt-c910, xt-c910v2, xt-c

Re: [PATCH v2]RISC-V:Add xuantie C908, C910, C920v1 and C920v2 to -mcpu

d the patch v3 fixing the c920v1 name issue. But it's ok for me that either of you and me to send the patch, If you have any concern please contact me. Best regards Yixuan Chen Jin Ma 于2025年3月20日周四 16:12写道： > On Mon, 17 Mar 2025 17:31:36 +0800, Yixuan Chen wrote: >

[PATCH v2]RISC-V:Add xuantie C908, C910, C920v1 and C920v2 to -mcpu

gcc/ChangeLog: * config/riscv/riscv-cores.def (RISCV_TUNE): Add xt-c908, xt-c910. (RISCV_CORE): Add xt-c908, xt-c910 and xt-c920v1 and xt-c920v2. * config/riscv/riscv.cc: Add xt-c908, xt-c910 tune info. * doc/invoke.texi: Add xt-c908, xt-c910 and xt-c920v1 and xt-c9

[PATCH]RISC-V:Add xuantie C909, C910, C920v1 and C920v2 to -mcpu

gcc/ChangeLog: * config/riscv/riscv-cores.def (RISCV_TUNE): Add xt-c908, xt-c910. (RISCV_CORE): Add xt-c908, xt-c910 and xt-c920v1 and xt-c920v2. * config/riscv/riscv.cc: Add xt-c908, xt-c910 tune info. * doc/invoke.texi: Add xt-c908, xt-c910 and xt-c920v1 and xt-c9

Re: [PATCH] minimal support for xtheadv

Hi Kito and Christoph, XYenChi (oriachi...@gmail.com) is my e-mail address too. I didn't notice the git email config have changed, very sorry about that. We want to support other operate system project from our team, so port the XTheadV. If T-Head and VRULL have made great progress, it's pleasure

[PATCH] Ver2: Riscv don't support "-fprefetch-loop-arrays" option, add "-w" option.

gcc/testsuite/ChangeLog: Riscv don't support "-fprefetch-loop-arrays" option, add "-w" option. 2022-11-22 Yixuan Chen * gcc.dg/pr106397.c: Riscv don't support "-fprefetch-loop-arrays" option, add "-w" option. --- gcc/testsuite/gc

[PATCH] Riscv don't support "-fprefetch-loop-arrays", skip.

gcc/testsuite/ChangeLog: Riscv don't support "-fprefetch-loop-arrays" option, skip. 2022-11-22 Yixuan Chen * gcc.dg/pr106397.c: Riscv don't support "-fprefetch-loop-arrays" option, skip. --- gcc/testsuite/gcc.dg/pr106397.c | 2 +- 1 file changed, 1 ins

[PATCH] optimize the testcase for architectures that use ".srodata"

2022-11-18 Yixuan Chen * gcc.dg/pr25521.c: optimize the testcast for architectures that use ".srodata" testsuite/gcc.dg/pr25521.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.dg/pr25521.c b/gcc/testsuite/gcc.dg/pr25521.c index 7

[PATCH] Ver.2: Add compile option "-msmall-data-limit=0" to avoid using .srodata section for riscv.

2022-11-17 Yixuan Chen * gcc/testsuite/gcc.dg/pr25521.c: Add compile option "-msmall-data-limit=0" to avoid using .srodata section for riscv. --- gcc/testsuite/gcc.dg/pr25521.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.dg/pr255

[PATCH] Optimize testcase

From: Oria Chen gcc/testsuite/ChangeLog: 2022-11-15 Yixuan Chen * gcc.dg/fold-overflow-1.c: Optimize testcase, because riscv will use ".LC0" intead of ".LC1" and ".LC2" with "-O" compile option --- gcc/testsuite/gcc.dg/fold-overflow-1.c | 3