Hi Majin, Thanks for your suggestion, Look like the document don't contain the following tune information: /* fmv_cost */, /* vector_unaligned_access */, /* use_divmod_expansion */, and /* overlap_op_by_pieces */ , I will follow your further modification and wait for the gcc16 window to send the patch v3 fixing the c920v1 name issue. But it's ok for me that either of you and me to send the patch, If you have any concern please contact me.
Best regards Yixuan Chen Jin Ma <ji...@linux.alibaba.com> 于2025年3月20日周四 16:12写道： > On Mon, 17 Mar 2025 17:31:36 +0800, Yixuan Chen wrote: > > gcc/ChangeLog: > > > > * config/riscv/riscv-cores.def (RISCV_TUNE): Add xt-c908, > xt-c910. > > (RISCV_CORE): Add xt-c908, xt-c910 and xt-c920v1 and xt-c920v2. > > * config/riscv/riscv.cc: Add xt-c908, xt-c910 tune info. > > * doc/invoke.texi: Add xt-c908, xt-c910 and xt-c920v1 and > xt-c920v2. > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/riscv/mcpu-xt-c908.c: New test. > > * gcc.target/riscv/mcpu-xt-c910.c: New test. > > * gcc.target/riscv/mcpu-xt-c920v1.c: New test. > > * gcc.target/riscv/mcpu-xt-c920v2.c: New test. > > > > Fix v1 Subject issue and ISA string issue. > > > > Add xuantie C909, C910, C920v1 and C920v2 to -mcpu > > Hi, Yixuan, > > I suggest changing C920v1 to C920, as this would better align with the > actual naming conventions of the CPU. > > > Tune info copied from: > https://github.com/XUANTIE-RV/gcc/blob/xuantie-gcc-10.2.0/gcc/config/riscv/riscv-xuantie-tune.h > > No C920 related tune info, use generic_ooo. > > This is feasible for now; we can make further modifications later. > > > Add xuantie C909, C910, C920v1 and C920v2 to -mcpu > > Tune info copied from: > https://github.com/XUANTIE-RV/gcc/blob/xuantie-gcc-10.2.0/gcc/config/riscv/riscv-xuantie-tune.h > > No C920 related tune info, use generic_ooo. > > --- > > gcc/config/riscv/riscv-cores.def | 25 ++++++++++++++ > > gcc/config/riscv/riscv.cc | 34 +++++++++++++++++++ > > gcc/doc/invoke.texi | 4 +-- > > gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c | 34 +++++++++++++++++++ > > gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c | 29 ++++++++++++++++ > > .../gcc.target/riscv/mcpu-xt-c920v1.c | 30 ++++++++++++++++ > > .../gcc.target/riscv/mcpu-xt-c920v2.c | 30 ++++++++++++++++ > > 7 files changed, 184 insertions(+), 2 deletions(-) > > create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v1.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c > > > > diff --git a/gcc/config/riscv/riscv-cores.def > b/gcc/config/riscv/riscv-cores.def > > index 2918496bcd0..af45ec57e90 100644 > > --- a/gcc/config/riscv/riscv-cores.def > > +++ b/gcc/config/riscv/riscv-cores.def > > @@ -41,6 +41,10 @@ RISCV_TUNE("sifive-p400-series", sifive_p400, > sifive_p400_tune_info) > > RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info) > > RISCV_TUNE("tt-ascalon-d8", generic_ooo, tt_ascalon_d8_tune_info) > > RISCV_TUNE("thead-c906", generic, thead_c906_tune_info) > > +RISCV_TUNE("xt-c908", generic, xt_c908_tune_info) > > +RISCV_TUNE("xt-c910", generic, xt_c910_tune_info) > > +RISCV_TUNE("xt-c920v1", generic, generic_ooo_tune_info) > > +RISCV_TUNE("xt-c920v2", generic, generic_ooo_tune_info) > > RISCV_TUNE("xiangshan-nanhu", xiangshan, xiangshan_nanhu_tune_info) > > RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info) > > RISCV_TUNE("size", generic, optimize_size_tune_info) > > @@ -93,6 +97,27 @@ RISCV_CORE("thead-c906", > "rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_" > > "xtheadmemidx_xtheadmempair_xtheadsync", > > "thead-c906") > > > > +RISCV_CORE("xt-c908", > "rv64imafdc_zihintpause_zfh_zba_zbb_zbc_zbs_" > > + "xtheadba_xtheadbb_xtheadbs_xtheadcmo_" > > + "xtheadcondmov_xtheadfmemidx_xtheadmac_" > > + "xtheadmemidx_xtheadmempair_xtheadsync", > > + "xt-c908") > > + > > +RISCV_CORE("xt-c910", > "rv64imafdc_zfh_xtheadba_xtheadbb_xtheadbs_xtheadcmo_" > > + > "xtheadcondmov_xtheadfmemidx_xtheadint_xtheadmac_" > > + "xtheadmemidx_xtheadmempair_xtheadsync", > > + "xt-c910") > > + > > +RISCV_CORE("xt-c920v1", > "rv64imafdc_zfh_xtheadba_xtheadbb_xtheadbs_xtheadcmo_" > > + > "xtheadcondmov_xtheadfmemidx_xtheadint_xtheadmac_" > > + > "xtheadmemidx_xtheadmempair_xtheadsync_xtheadvector", > > + "xt-c920v1") > > + > > +RISCV_CORE("xt-c920v2", > "rv64imafdcv_zfh_xtheadba_xtheadbb_xtheadbs_xtheadcmo_" > > + > "xtheadcondmov_xtheadfmemidx_xtheadint_xtheadmac_" > > + "xtheadmemidx_xtheadmempair_xtheadsync", > > + "xt-c920v2") > > + > > We can add the extension xtheadfmv to all of these models. Additionally, > the C920v2 also supports zfa, zfbfmin, zcb, zba, zbb, zbc, zbs, zvfbfmin, > zvfbfwma, and zvfh. > > > RISCV_CORE("tt-ascalon-d8", "rv64imafdcv_zic64b_zicbom_zicbop_zicboz_" > > > "ziccamoa_ziccif_zicclsm_ziccrse_zicond_zicsr_" > > > "zifencei_zihintntl_zihintpause_zimop_za64rs_" > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > > index 38f3ae7cd84..3dfb0a71f88 100644 > > --- a/gcc/config/riscv/riscv.cc > > +++ b/gcc/config/riscv/riscv.cc > > @@ -554,6 +554,40 @@ static const struct riscv_tune_param > thead_c906_tune_info = { > > NULL, /* loop_align */ > > }; > > > > +/* Costs to use when optimizing for xuantie C908. */ > > +const struct riscv_tune_param xt_c908_tune_info = { > > + {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */ > > + {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */ > > + {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */ > > + {COSTS_N_INSNS (3), COSTS_N_INSNS (3)}, /* int_mul */ > > + {COSTS_N_INSNS (16), COSTS_N_INSNS (16)}, /* int_div */ > > + 2, /* issue_rate */ > > + 3, /* branch_cost */ > > + 5, /* memory_cost */ > > + > > + false, /* > slow_unaligned_access */ > > + "16", /* function_align */ > > + "8", /* jump_align */ > > + "8", /* loop_align */ > > +}; > > It seems like a lot of important information is missing here, such as > /* fmv_cost */, /* vector_unaligned_access */, /* use_divmod_expansion */, > and /* overlap_op_by_pieces */. > > Without these, it likely won’t be possible to build the toolchain > correctly. :) > > > + > > +/* Costs to use when optimizing for xuantie C910. */ > > +const struct riscv_tune_param xt_c910_tune_info = { > > + {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */ > > + {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */ > > + {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */ > > + {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */ > > + {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */ > > + 1, /* issue_rate */ > > + 3, /* branch_cost */ > > + 5, /* memory_cost */ > > + > > + false, /* slow_unaligned_access */ > > + "16", /* function_align > */ > > + "4", /* jump_align */ > > + "8", /* loop_align */ > > +}; > > + > > /* Costs to use when optimizing for xiangshan nanhu. */ > > static const struct riscv_tune_param xiangshan_nanhu_tune_info = { > > {COSTS_N_INSNS (3), COSTS_N_INSNS (3)}, /* fp_add */ > > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > > index 4fbb4cda101..74e423b3c0e 100644 > > --- a/gcc/doc/invoke.texi > > +++ b/gcc/doc/invoke.texi > > @@ -31329,8 +31329,8 @@ Permissible values for this option are: > @samp{sifive-e20}, @samp{sifive-e21}, > > @samp{sifive-e24}, @samp{sifive-e31}, @samp{sifive-e34}, > @samp{sifive-e76}, > > @samp{sifive-s21}, @samp{sifive-s51}, @samp{sifive-s54}, > @samp{sifive-s76}, > > @samp{sifive-u54}, @samp{sifive-u74}, @samp{sifive-x280}, > @samp{sifive-xp450}, > > -@samp{sifive-x670}, @samp{thead-c906}, @samp{tt-ascalon-d8}, > > -@samp{xiangshan-nanhu}. > > +@samp{sifive-x670}, @samp{thead-c906}, @samp{tt-ascalon-d8}, > @samp{xiangshan-nanhu}, > > +@samp{xt-c908}, @samp{xt-c910}, @samp{xt-c920v1}, @samp{xt-c920v2}. > > > > Note that @option{-mcpu} does not override @option{-march} or > @option{-mtune}. > > > > diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c > b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c > > new file mode 100644 > > index 00000000000..9370f7e63d0 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c > > @@ -0,0 +1,34 @@ > > +/* { dg-do compile } */ > > +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ > > +/* { dg-options "-mcpu=xt-c908" { target { rv64 } } } */ > > +/* XuanTie C908 => > rv64imafdc_zba_zbb_zbc_zbs_zfh_xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_xtheadmemidx_xtheadmempair_xtheadsync_zihintpause > */ > > + > > +#if !((__riscv_xlen == 64) \ > > + && !defined(__riscv_32e) \ > > + && defined(__riscv_mul) \ > > + && defined(__riscv_atomic) \ > > + && (__riscv_flen == 64) \ > > + && defined(__riscv_compressed) \ > > + && defined(__riscv_zihintpause) \ > > + && defined(__riscv_zba) \ > > + && defined(__riscv_zbb) \ > > + && defined(__riscv_zbc) \ > > + && defined(__riscv_zbs) \ > > + && defined(__riscv_zfh) \ > > + && defined(__riscv_xtheadba) \ > > + && defined(__riscv_xtheadbb) \ > > + && defined(__riscv_xtheadbs) \ > > + && defined(__riscv_xtheadcmo) \ > > + && defined(__riscv_xtheadcondmov) \ > > + && defined(__riscv_xtheadfmemidx) \ > > + && defined(__riscv_xtheadmac) \ > > + && defined(__riscv_xtheadmemidx) \ > > + && defined(__riscv_xtheadmempair) \ > > + && defined(__riscv_xtheadsync)) > > +#error "unexpected arch" > > +#endif > > + > > +int main() > > +{ > > + return 0; > > +} > > diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c > b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c > > new file mode 100644 > > index 00000000000..7a813c3071e > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c > > @@ -0,0 +1,29 @@ > > +/* { dg-do compile } */ > > +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ > > +/* { dg-options "-mcpu=xt-c910" { target { rv64 } } } */ > > +/* XuanTie C910 => > rv64imafdc_zfh_xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadint_xtheadmac_xtheadmemidx_xtheadmempair_xtheadsync > */ > > + > > +#if !((__riscv_xlen == 64) \ > > + && !defined(__riscv_32e) \ > > + && defined(__riscv_mul) \ > > + && defined(__riscv_atomic) \ > > + && (__riscv_flen == 64) \ > > + && defined(__riscv_compressed) \ > > + && defined(__riscv_zfh) \ > > + && defined(__riscv_xtheadba) \ > > + && defined(__riscv_xtheadbb) \ > > + && defined(__riscv_xtheadbs) \ > > + && defined(__riscv_xtheadcmo) \ > > + && defined(__riscv_xtheadcondmov) \ > > + && defined(__riscv_xtheadfmemidx) \ > > + && defined(__riscv_xtheadmac) \ > > + && defined(__riscv_xtheadmemidx) \ > > + && defined(__riscv_xtheadmempair) \ > > + && defined(__riscv_xtheadsync)) > > +#error "unexpected arch" > > +#endif > > + > > +int main() > > +{ > > + return 0; > > +} > > diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v1.c > b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v1.c > > new file mode 100644 > > index 00000000000..f81d6c2e99c > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v1.c > > @@ -0,0 +1,30 @@ > > +/* { dg-do compile } */ > > +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ > > +/* { dg-options "-mcpu=xt-c920v1" { target { rv64 } } } */ > > +/* XuanTie c920v1 => > rv64imafdc_zfh_xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadint_xtheadmac_xtheadmemidx_xtheadmempair_xtheadsync_xtheadvector > */ > > + > > +#if !((__riscv_xlen == 64) \ > > + && !defined(__riscv_32e) \ > > + && defined(__riscv_mul) \ > > + && defined(__riscv_atomic) \ > > + && (__riscv_flen == 64) \ > > + && defined(__riscv_compressed) \ > > + && defined(__riscv_zfh) \ > > + && defined(__riscv_xtheadba) \ > > + && defined(__riscv_xtheadbb) \ > > + && defined(__riscv_xtheadbs) \ > > + && defined(__riscv_xtheadcmo) \ > > + && defined(__riscv_xtheadcondmov) \ > > + && defined(__riscv_xtheadfmemidx) \ > > + && defined(__riscv_xtheadmac) \ > > + && defined(__riscv_xtheadmemidx) \ > > + && defined(__riscv_xtheadmempair) \ > > + && defined(__riscv_xtheadsync)) \ > > + && defined(__riscv_xtheadvector) > > +#error "unexpected arch" > > +#endif > > + > > +int main() > > +{ > > + return 0; > > +} > > diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c > b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c > > new file mode 100644 > > index 00000000000..bd3a06aad49 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c > > @@ -0,0 +1,30 @@ > > +/* { dg-do compile } */ > > +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ > > +/* { dg-options "-mcpu=xt-c906" { target { rv64 } } } */ > > +/* XuanTie C920v2 => > rv64imafdcv_zfh_xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadint_xtheadmac_xtheadmemidx_xtheadmempair_xtheadsync > */ > > + > > +#if !((__riscv_xlen == 64) \ > > + && !defined(__riscv_32e) \ > > + && defined(__riscv_mul) \ > > + && defined(__riscv_atomic) \ > > + && (__riscv_flen == 64) \ > > + && defined(__riscv_compressed) \ > > + && defined(__riscv_v) \ > > + && defined(__riscv_zfh) \ > > + && defined(__riscv_xtheadba) \ > > + && defined(__riscv_xtheadbb) \ > > + && defined(__riscv_xtheadbs) \ > > + && defined(__riscv_xtheadcmo) \ > > + && defined(__riscv_xtheadcondmov) \ > > + && defined(__riscv_xtheadfmemidx) \ > > + && defined(__riscv_xtheadmac) \ > > + && defined(__riscv_xtheadmemidx) \ > > + && defined(__riscv_xtheadmempair) \ > > + && defined(__riscv_xtheadsync)) > > +#error "unexpected arch" > > +#endif > > + > > +int main() > > +{ > > + return 0; > > +} > > -- > > 2.47.1 > > Overall, it’s great! You can refer to the relevant manual for more > information. > > https://www.xrvm.cn/community/download?id=4224248662731067392 > > Best regards, > Jin Ma
