> On 30 Jun 2025, at 17:55, Alfie Richards wrote:
>
> On 29/06/2025 19:57, Yangyu Chen wrote:
>> This patch adds support for target_clones table option. The
>> target_clones table option allows users to specify multiple versions
>> of a function and select the vers
pool.
This patch removes the make_decl_rtl call in trans_function_start, and
it will finally be called in all my testcases since we will check it
whenever using the DECL_RTL macro.
Signed-off-by: Yangyu Chen
gcc/fortran/ChangeLog:
* trans-decl.cc (trans_function_start): Remove call
able=ror32.target_clones -S ror32.c
to compile the source code. This will generate 3 versions and its IFUNC
resolver for the ror32 function which is "arch=+zvbb,+zbb" and
"arch=+zbb" and the default version.
Signed-off-by: Yangyu Chen
gcc/ChangeLog:
* Makefile.in: Add
Currently, the object class in json.h does not provide a way to iterate
over its keys. This commit adds an `iterate` method to the object class,
allowing users to iterate over the keys of a JSON object.
Signed-off-by: Yangyu Chen
gcc/ChangeLog:
* json.h (class object): Add iterate
. Can specify
multiple target clones attributes in a single JSON table, which
makes it more flexible and easier to use.
v1:
https://patchwork.sourceware.org/project/gcc/cover/tencent_7e345ef1390b9a68a738cee15ec510864...@qq.com/
Yangyu Chen (3):
Fortran: Do not make_decl_rtl in trans_funct
On 18/6/2025 09:07, Kito Cheng wrote:
Maybe it's a good time to create a -mtune=generic and copy-and-modify
from rocket?
Indeed, it appears to be the most suitable solution.
Thanks,
Yangyu Chen
On Wed, Jun 18, 2025 at 6:59 AM Jeff Law wrote:
On 6/17/25 10:51 AM, Yangyu Chen
sprediction on large OoO cores usually incurs a penalty of about 10
cycles.
Thanks,
Yangyu Chen
WRT a followup from Yangyu which touches on the BPI. My son is
currently putting together a tuning and scheduler model for the spacemit
x60 chip in that system under my guidance. I expect we'll
On 17/6/2025 12:08, Dongyan Chen wrote:
Hi, I've come across a question regarding the branch cost of gcc. In the link
https://gcc.godbolt.org/z/hnddevd5h, gcc fails to recognize the optimization
branch judgment, while llvm does. I eventually discovered that the value of the
branch
cost was to
_zknh_zksed_zksh_zkt_zvbb_zvfh_"
>> + "zvfhmin_zvkt_zvl128b_zvl32b_zvl64b",
>
> IIUC zvl128b implies zvl32b and zvl64b, then should we explicitly give
> zvl32b and zvl64b here?
I think not. Other existing cores in GCC are also not giving implied
zvl* here.
The implied ISAs will be handled automatically by GCC, thus we don't
need to specify them.
Thanks,
Yangyu Chen
>
>> + "xiangshan-kunminghu")
>
> --
> Xi Ruoyao
> School of Aerospace Science and Technology, Xidian University
> On 27 May 2025, at 20:59, Jeff Law wrote:
> So if it's OK with you I'd like to temporarily shift focus over to Alfie's
> patch to get that moved forward, then come back to the RISC-V specific stuff?
>
Sure.
Thanks,
Yangyu Chen
> Jeff
>
would
> still be relevant if we incorporated Alfie's work?
>
I agree with Alfie's approach. We are addressing the same issue.
His patch is more structured and includes test cases.
His patch lacks a target hook for RISC-V, while mine does. However,
I think it's OK if we get his patch accepted, and I will write that
for RISC-V.
Thanks,
Yangyu Chen
> On 15 May 2025, at 14:01, Alice Carlotti wrote:
>
> On Thu, May 08, 2025 at 09:41:08PM +0800, Yangyu Chen wrote:
>>
>>
>>> On 8 May 2025, at 18:36, Richard Sandiford
>>> wrote:
>>>
>>> Yangyu Chen writes:
>>>>> On
We should also back-port this commit to GCC-14.
Thanks,
Yangyu Chen
On 6/9/2024 07:07, Zhao Dingyi wrote:
This patch aims to add the missing instruction types to the XiangShan-Nanhu
scheduler model.
The current XiangShan -Nanhu model lacks the trap, atomic trap, fcvt_i2f, and
fcvt_f2i
> On 8 May 2025, at 18:36, Richard Sandiford wrote:
>
> Yangyu Chen writes:
>>> On 6 May 2025, at 17:49, Alfie Richards wrote:
>>>
>>> On 06/05/2025 09:36, Yangyu Chen wrote:
>>>>> On 6 May 2025, at 16:01, Alfie Richards wrote:
>
> On 6 May 2025, at 17:49, Alfie Richards wrote:
>
> On 06/05/2025 09:36, Yangyu Chen wrote:
>>> On 6 May 2025, at 16:01, Alfie Richards wrote:
>>>
>>> Hello,
>>>
>>> I like this idea. I have a couple thoughts to add.
>>>
>
> On 6 May 2025, at 16:01, Alfie Richards wrote:
>
> Hello,
>
> I like this idea. I have a couple thoughts to add.
>
> On 05/05/2025 09:46, Yangyu Chen wrote:
>>> On 5 May 2025, at 16:34, Kyrylo Tkachov wrote:
>>>
>>>> On 4 May 2025, a
> On 5 May 2025, at 16:34, Kyrylo Tkachov wrote:
>
>
>
>> On 4 May 2025, at 19:19, Yangyu Chen wrote:
>>
>> Hi everyone,
>>
>> This patch series introduces support for the target_clones profile
>> option in GCC. This option enables u
them.
However, I would appreciate feedback on the implementation before
adding them. If the implementation is deemed acceptable, I
will proceed with writing the documentation and test cases.
Yangyu Chen (2):
Fortran: Do not make_decl_rtl in trans_function_start
Add target_clones profile o
the ror32 function which is "arch=+zvbb,+zbb" and
"arch=+zbb" and the default version.
Signed-off-by: Yangyu Chen
gcc/ChangeLog:
* common.opt: Add target_clones profile option.
* multiple_target.cc (expand_target_clones): Add support for
target_clones
pool.
This patch removes the make_decl_rtl call in trans_function_start, and
it will finally be called in all my testcases since we will check it
whenever using the DECL_RTL macro.
Signed-off-by: Yangyu Chen
gcc/fortran/ChangeLog:
* trans-decl.cc (trans_function_start): Remove call
aller is
> versioned. I will share this with you shortly and we can work out what we
> wish to use?
Sure! Thank you!
Thanks,
Yangyu Chen
>
> Kind regards,
> Alfie
>
> On 14/04/2025 10:00, Yangyu Chen wrote:
>> This patchset implements a new featu
with the current caller version and
redirects to it.
This mechanism has been discussed in a previous patch [1].
[1] https://patchwork.sourceware.org/comment/197172/
Signed-off-by: Yangyu Chen
gcc/ChangeLog:
* doc/tm.texi: New Target Hook TARGET_VERSION_COMPATIBLE.
* doc
version for RISC-V architectures.
[1] https://patchwork.sourceware.org/comment/197172/
Yangyu Chen (3):
Redirect to specific target based on TARGET_VERSION_COMPATIBLE
RISC-V: Split parse_features_for_version with cl_target_option
returned
RISC-V: Implement TARGET_VERSION_COMPATIBLE
gcc
On 14/4/2025 17:02, Yangyu Chen wrote:
This commit introduces a new target hook, TARGET_VERSION_COMPATIBLE,
enabling the redirection of specific target clones based on version
compatibility. Additionally, it modifies the existing redirection
mechanism to support this new hook, which
-by: Yangyu Chen
gcc/ChangeLog:
* config/riscv/riscv.cc (parse_features_for_version): Split
parse_features_for_version with cl_target_option returned.
---
gcc/config/riscv/riscv.cc | 60 ---
1 file changed, 37 insertions(+), 23 deletions
This patch implements the TARGET_VERSION_COMPATIBLE macro for RISC-V.
It checks if the versioned callee is compatible with the versioned
caller.
Signed-off-by: Yangyu Chen
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_version_compatible): New function
_target.cc (redirect_to_specific_clone): Support
RISC-V FMV redirect.
(ipa_target_clone): Check TARGET_FMV_REDIRECT_CLONE.
Signed-off-by: Yangyu Chen
---
There is a problem raised in the previous discussion [1]: This behavior
will eliminate the indirection in some cases where the runtime
(parse_res == AARCH_PARSE_OK);
> + parse_res = aarch64_parse_fmv_features (str2, NULL,
> + &feature_mask2, NULL);
> + gcc_assert (parse_res == AARCH_PARSE_OK);
>
> - return (aarch64_compare_version_priority (fn1, fn2) != 0);
> + return feature_mask1 == feature_mask2;
&g
Hi Alfie,
It appears that you've duplicated patch 14/19. The only difference
between them is the title, which replaces "and" with "in order to".
I think the latter version is what you intended.
Thanks,
Yangyu Chen
> On 27 Mar 2025, at 16:45, Alfie Richards wrote:
>
>
> Notably this respects target_version semantics where an unannotated
> function can be the default version.
>
> gcc/ChangeLog:
>
> * attribs.cc (is_function_default_version): Add target_version logic.
> ---
> gcc/attribs.cc | 27 +++
On 25/3/2025 21:23, Kito Cheng wrote:
Will it only cause issues with this patch
https://gcc.gnu.org/pipermail/gcc-patches/2025-March/678918.html
Yes. But I think we can merge this first.
Thanks,
Yangyu Chen
or will it cause problems with the current trunk as well?
If the latter one
name mangling.
Signed-off-by: Yangyu Chen
---
gcc/config/riscv/riscv.cc | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 38f3ae7cd84..4a042878554 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/ris
> On 24 Mar 2025, at 16:28, Alfie Richards wrote:
>
> On 24/03/2025 03:28, Yangyu Chen wrote:
>>> On 24 Mar 2025, at 11:03, Andrew Carlotti wrote:
>>>
>>> Two brief comments, since I'm on holiday until 31st but happened to notice
>>> this
> On 24 Mar 2025, at 11:03, Andrew Carlotti wrote:
>
> Two brief comments, since I'm on holiday until 31st but happened to notice
> this
> patch anyway.
>
> On Mon, Mar 24, 2025 at 02:19:21AM +0800, Yangyu Chen wrote:
>> This behavior does not ensure th
On 20/2/2025 16:31, Dongyan Chen wrote:
This patch support Qualcomm uC Xqccmp extension[1].
To enable GCC to recognize and process xqccmp extension correctly at compile
time.
[1]https://github.com/quic/riscv-unified-db/releases/tag/Xqccmp_extension-0.1.0
gcc/ChangeLog:
* common/con
-off-by: Yangyu Chen
gcc/ChangeLog:
* config/riscv/riscv-feature-bits.h (RISCV_VENDOR_FEATURE_BITS_LENGTH):
Drop.
(struct riscv_vendor_feature_bits): Drop.
libgcc/ChangeLog:
* config/riscv/feature_bits.c (RISCV_VENDOR_FEATURE_BITS_LENGTH): Drop
----
There was a previous patch by Yangyu Chen [1] which addressed flaw 1 but
overlooked flaw 2. I pointed out flaw 2 at the time; as far as I can tell,
there haven't been any further patches proposed for this issue (apologies if I
missed something; I've not checked the mailing lists parti
("RISC-V: Minimal support for svvptc extension.")
Signed-off-by: Yangyu Chen
gcc/ChangeLog:
* common/config/riscv/riscv-ext-bitmask.def (RISCV_EXT_BITMASK): Remove
svvptc.
---
gcc/common/config/riscv/riscv-ext-bitmask.def | 1 -
1 file changed, 1 deletion(-)
diff --git a/
subext, MASK_ZCLSD),
>>
>> RISCV_EXT_FLAG_ENTRY ("svinval", x_riscv_sv_subext, MASK_SVINVAL),
>> RISCV_EXT_FLAG_ENTRY ("svnapot", x_riscv_sv_subext, MASK_SVNAPOT),
>> diff --git a/gcc/common/config/riscv/riscv-ext-bitmask.def
>> b/gcc/common/
Ping again.
On 11/5/24 11:37, Yangyu Chen wrote:
Ping and also CC Jeff and Kito. This is also useful for RISC-V since
RISC-V uses target_version, which defines
TARGET_HAS_FMV_TARGET_ATTRIBUTE to zero.
On 10/28/24 00:00, Yangyu Chen wrote:
Following the implementation of commit b8ce8129a5
Sorry for the wrong address CC to Yulong.
And this should add fixes:
Fixes: 4bee5252c1de ("RISC-V: Add norelax function attribute")
The target-attr-norelax.c testcase was failing due to the redundant "\t"
check in the assembly output, and forgot to skip the check for lto build
in the testcase.
Signed-off-by: Yangyu Chen
gcc/testsuite/ChangeLog:
* gcc.target/riscv/target-attr-norelax.c: Fix testcase
Thanks for doing this!
> On Nov 8, 2024, at 00:19, shiyul...@iscas.ac.cn wrote:
>
> From: yulong
>
> This patch adds norelax function attribute that be discussed in
> riscv-c-api-doc PR#94.
> URL:https://github.com/riscv-non-isa/riscv-c-api-doc/pull/94
>
> gcc/ChangeLog:
>
>* config/
Ping and also CC Jeff and Kito. This is also useful for RISC-V since
RISC-V uses target_version, which defines
TARGET_HAS_FMV_TARGET_ATTRIBUTE to zero.
On 10/28/24 00:00, Yangyu Chen wrote:
Following the implementation of commit b8ce8129a5 ("Redirect call
within specific target attr
reuses the code
in TARGET_COMPARE_VERSION_PRIORITY and check it returns 0, which means
the equal priority.
Co-Developed-by: Hank Chang
Signed-off-by: Yangyu Chen
gcc/ChangeLog:
* config/riscv/riscv.cc
(parse_features_for_version): New function.
(compare_fmv_features
ent in the dispatcher function.
Signed-off-by: Yangyu Chen
gcc/ChangeLog:
* config/riscv/riscv.cc (add_condition_to_bb): New function.
(dispatch_function_versions): New function.
(get_suffixed_assembler_name): New function.
(make_resolver_func): Ne
et_version"
for function versioning.
Co-Developed-by: Hank Chang
Signed-off-by: Yangyu Chen
gcc/ChangeLog:
* config/riscv/riscv-protos.h
(riscv_process_target_attr): Remove as it is not used.
(riscv_option_valid_version_attribute_p): Declare.
(riscv_process
This patch adds test cases for the Function Multi-Versioning (FMV)
feature for RISC-V, which reuses the existing test cases from the
aarch64 and ported them to RISC-V.
Signed-off-by: Yangyu Chen
gcc/testsuite/ChangeLog:
* g++.target/riscv/mv-symbols1.C: New test.
* g++.target
This patch implements the TARGET_MANGLE_DECL_ASSEMBLER_NAME for RISC-V.
This is used to add function multiversioning suffixes to the assembler
name.
Signed-off-by: Yangyu Chen
gcc/ChangeLog:
* config/riscv/riscv.cc
(riscv_mangle_decl_assembler_name): New function
/85
Signed-off-by: Yangyu Chen
gcc/ChangeLog:
* config/riscv/riscv-target-attr.cc
(riscv_target_attr_parser::handle_priority): New function.
(riscv_target_attr_parser::update_settings): Update priority
attribute.
* config/riscv/riscv.opt: Add TargetVariable
g to allow the FMV dispatcher to work correctly on older
kernels.
Signed-off-by: Yangyu Chen
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc
(RISCV_EXT_BITMASK): New macro.
(struct riscv_ext_bitmask_table_t): New struct.
(riscv_minimal_hwprobe_feature_bits): Ne
the separator,
since '#' is not allowed in the target_clones option string.
[1]
https://github.com/riscv-non-isa/riscv-c-api-doc/blob/c6c5d6d9cf96b342293315a5dff3d25e96ef8191/src/c-api.adoc#__attribute__targetattr-string
Signed-off-by: Yangyu Chen
gcc/ChangeLog:
* defaults.
3cRNDuSNp58Tgpt=pzm4dg...@mail.gmail.com/
[5]
https://inbox.sourceware.org/gcc-patches/tencent_fd68a30bdf936092b6a663146e634c76c...@qq.com/
[6]
https://inbox.sourceware.org/gcc-patches/tencent_a646c713dc9218dd10ca460ebe074153e...@qq.com/
[7]
https://patchwork.sourceware.org/project/gcc/patch/tencent_
This patch adds test cases for the Function Multi-Versioning (FMV)
feature for RISC-V, which reuses the existing test cases from the
aarch64 and ported them to RISC-V.
Signed-off-by: Yangyu Chen
gcc/testsuite/ChangeLog:
* g++.target/riscv/mv-symbols1.C: New test.
* g++.target
This patch implements the TARGET_MANGLE_DECL_ASSEMBLER_NAME for RISC-V.
This is used to add function multiversioning suffixes to the assembler
name.
Signed-off-by: Yangyu Chen
gcc/ChangeLog:
* config/riscv/riscv.cc
(riscv_mangle_decl_assembler_name): New function
reuses the code
in TARGET_COMPARE_VERSION_PRIORITY and check it returns 0, which means
the equal priority.
Co-Developed-by: Hank Chang
Signed-off-by: Yangyu Chen
gcc/ChangeLog:
* config/riscv/riscv.cc
(parse_features_for_version): New function.
(compare_fmv_features
ent in the dispatcher function.
Signed-off-by: Yangyu Chen
gcc/ChangeLog:
* config/riscv/riscv.cc (add_condition_to_bb): New function.
(dispatch_function_versions): New function.
(get_suffixed_assembler_name): New function.
(make_resolver_func): Ne
et_version"
for function versioning.
Co-Developed-by: Hank Chang
Signed-off-by: Yangyu Chen
gcc/ChangeLog:
* config/riscv/riscv-protos.h
(riscv_process_target_attr): Remove as it is not used.
(riscv_option_valid_version_attribute_p): Declare.
(riscv_process
g to allow the FMV dispatcher to work correctly on older
kernels.
Signed-off-by: Yangyu Chen
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc
(RISCV_EXT_BITMASK): New macro.
(struct riscv_ext_bitmask_table_t): New struct.
(riscv_minimal_hwprobe_feature_bits): Ne
/85
Signed-off-by: Yangyu Chen
gcc/ChangeLog:
* config/riscv/riscv-target-attr.cc
(riscv_target_attr_parser::handle_priority): New function.
(riscv_target_attr_parser::update_settings): Update priority
attribute.
* config/riscv/riscv.opt: Add TargetVariable
the separator,
since '#' is not allowed in the target_clones option string.
[1]
https://github.com/riscv-non-isa/riscv-c-api-doc/blob/c6c5d6d9cf96b342293315a5dff3d25e96ef8191/src/c-api.adoc#__attribute__targetattr-string
Signed-off-by: Yangyu Chen
gcc/ChangeLog:
* defaults.
m/
[6]
https://inbox.sourceware.org/gcc-patches/tencent_a646c713dc9218dd10ca460ebe074153e...@qq.com/
[7]
https://patchwork.sourceware.org/project/gcc/patch/tencent_f08be088f6b1e3152e508c63c870e31cd...@qq.com/
Yangyu Chen (8):
Introduce TARGET_CLONES_ATTR_SEPARATOR for RISC-V
RISC-V: Implement Priority synt
On 10/31/24 21:26, Kito Cheng wrote:
On Thu, Oct 31, 2024 at 6:59 PM Yangyu Chen wrote:
On Oct 31, 2024, at 18:14, Kito Cheng wrote:
diff --git a/gcc/config/riscv/riscv-target-attr.cc
b/gcc/config/riscv/riscv-target-attr.cc
index 087fbae77b0..4c85ad60b72 100644
--- a/gcc/config/riscv
after checking all the callers for
target_option,valid_attribute_p, I see that this case is already being
handled, so it dropped.
On Thu, Oct 24, 2024 at 3:15 PM Yangyu Chen wrote:
To ensure that the target_version attribute is applied after target
attributes.
gcc/ChangeLog
discussion, a possible solution might be to refuse the
relax for the IFUNC resolvers and its callees. Thus, we don’t require
gp to access global variables like __riscv_feature_bits.
I came up with a solution that adds an attribute like
__attribute__((norelax)) to functional like -mno-relax for a specific
function to both the FMV resolver gimple function and the libgcc
source code which will be called from FMV resolver.
Would this solution be acceptable?
Thanks,
Yangyu Chen
> On Oct 31, 2024, at 18:14, Kito Cheng wrote:
>
>> diff --git a/gcc/config/riscv/riscv-target-attr.cc
>> b/gcc/config/riscv/riscv-target-attr.cc
>> index 087fbae77b0..4c85ad60b72 100644
>> --- a/gcc/config/riscv/riscv-target-attr.cc
>> +++ b/gcc/config/riscv/riscv-target-attr.cc
>> @@ -239,1
NC resolver.
> so I guess we need to make riscv_target_attr_parser able to
> distinguish target and target_version? maybe add an extra argument to
> riscv_target_attr_parser?
I think so if it really needed.
>
> On Thu, Oct 24, 2024 at 3:12 PM Yangyu Chen wrote:
>>
>&
: Yangyu Chen
gcc/ChangeLog:
* config/riscv/predicates.md: Use flag_plt instead of TARGET_PLT.
* config/riscv/riscv.opt: alias common option fplt to mplt.
---
gcc/config/riscv/predicates.md | 2 +-
gcc/config/riscv/riscv.opt | 4 ++--
2 files changed, 3 insertions(+), 3 deletions
x27;s safe to use logical and to combine them.
Co-Developed-by: Liao Shihua
Signed-off-by: Yangyu Chen
gcc/ChangeLog:
* config/riscv/predicates.md: deprecates mplt option.
* config/riscv/riscv.opt: allow -fno-plt to disable PLT.
---
gcc/config/riscv/predicates.md | 3 ++-
gcc/c
> On Oct 30, 2024, at 19:59, Richard Sandiford
> wrote:
>
> Yangyu Chen writes:
>> We forgot to apply DECL_EXTERNAL to __init_cpu_features_resolver decl. When
>> building with LTO, the linker cannot find the
>> __init_cpu_features_resolver.lto_priv*
: 0cfde688e213 ("[aarch64] Add function multiversioning support")
Signed-off-by: Yangyu Chen
gcc/ChangeLog:
* config/aarch64/aarch64.cc (dispatch_function_versions): Adding
DECL_EXTERNAL, TREE_PUBLIC and hidden DECL_VISIBILITY to
__init_cpu_features_resolver and
We forgot to apply DECL_EXTERNAL to __init_cpu_features_resolver decl. When
building with LTO, the linker cannot find the
__init_cpu_features_resolver.lto_priv* symbol, causing the link error.
This patch gets this fixed by adding DECL_EXTERNAL to the decl. To avoid used
but never defined warning f
Following the implementation of commit b8ce8129a5 ("Redirect call
within specific target attribute among MV clones (PR ipa/82625)"),
we can now optimize calls by invoking a versioned function callee
from a caller that shares the same target attribute. However, on
targets that define TARGET_HAS_FMV_
Following the implementation of commit b8ce8129a5 ("Redirect call
within specific target attribute among MV clones (PR ipa/82625)"),
we can now optimize calls by invoking a versioned function callee
from a caller that shares the same target attribute. However, on
targets that define TARGET_HAS_FMV_
We forgot to apply DECL_EXTERNAL to __init_cpu_features_resolver decl. When
building with LTO, the linker cannot find the
__init_cpu_features_resolver.lto_priv* symbol, causing the link error.
This patch get this fixed by adding DECL_EXTERNAL to the decl. To avoid used but
never defined warning fo
On 2024/10/24 15:13, Yangyu Chen wrote:
This patch implements the TARGET_GENERATE_VERSION_DISPATCHER_BODY and
TARGET_GET_FUNCTION_VERSIONS_DISPATCHER for RISC-V. This is used to
generate the dispatcher function and get the dispatcher function for
function multiversioning.
This patch copies
We forgot to apply DECL_EXTERNAL to __init_cpu_features_resolver decl. When
building with LTO, the linker cannot find the
__init_cpu_features_resolver.lto_priv* symbol, causing the link error.
This patch get this fixed by adding DECL_EXTERNAL to the decl.
Minimal steps to reproduce the bug:
echo
re. I’ve also been testing these patches recently since one of my research
works relies on this.
FYI, there is a v3 version now.
Link: https://patchwork.sourceware.org/project/gcc/list/?series=39863&state=*
Thanks,
Yangyu Chen
> On Mon, Oct 21, 2024 at 11:57 AM Yangyu Chen wrote:
>>
This patch implements the TARGET_GENERATE_VERSION_DISPATCHER_BODY and
TARGET_GET_FUNCTION_VERSIONS_DISPATCHER for RISC-V. This is used to
generate the dispatcher function and get the dispatcher function for
function multiversioning.
This patch copies many codes from commit 0cfde688e213 ("[aarch64]
When the callee is versioned but the caller is not, we should not inline
the callee into the caller, to prevent the default version of the callee
from being inlined into a not versioned caller.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_can_inline_p): Refuse to inline
when call
This patch adds test cases for the Function Multi-Versioning (FMV)
feature for RISC-V, which reuses the existing test cases from the
aarch64 and ported them to RISC-V.
gcc/testsuite/ChangeLog:
* g++.target/riscv/mv-symbols1.C: New test.
* g++.target/riscv/mv-symbols2.C: New test.
To ensure that the target_version attribute is applied after target
attributes.
gcc/ChangeLog:
* config/riscv/riscv-target-attr.cc
(riscv_option_valid_attribute_p): Reapply target_version
attribute after target attribute
---
gcc/config/riscv/riscv-target-attr.cc | 13
This patch implements TARGET_COMPARE_VERSION_PRIORITY and
TARGET_OPTION_FUNCTION_VERSIONS for RISC-V.
The TARGET_COMPARE_VERSION_PRIORITY is implemented to compare the
priority of two function versions based on the rules defined in the
RISC-V C-API Doc PR #85:
https://github.com/riscv-non-isa/ris
This patch implements the TARGET_MANGLE_DECL_ASSEMBLER_NAME for RISC-V.
This is used to add function multiversioning suffixes to the assembler
name.
gcc/ChangeLog:
* config/riscv/riscv.cc
(riscv_mangle_decl_assembler_name): New function.
(TARGET_MANGLE_DECL_ASSEMBLER_NAME)
This patch implements the TARGET_OPTION_VALID_VERSION_ATTRIBUTE_P for
RISC-V. This hook is used to process attribute
((target_version ("..."))).
Co-Developed-by: Hank Chang
gcc/ChangeLog:
* config/riscv/riscv-protos.h
(riscv_option_valid_version_attribute_p): Declare.
(r
v-ext-bitmask.def
@@ -0,0 +1,83 @@
+/* RISC-V Extension Bitmask Definitions, corresponding to Extension Bitmask
+ Definitions in RISC-V C API Specification.
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ Contributed by Yangyu Chen (c...@cyyself.name).
+
+This file is part of GCC.
+
+
This patch adds the priority syntax parser to support the Function
Multi-Versioning (FMV) feature in RISC-V. This feature allows users to
specify the priority of the function version in the attribute syntax.
Chnages based on RISC-V C-API PR:
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/85
This patch splits static bool riscv_process_target_attr
(tree args, location_t loc) into two functions:
- bool riscv_process_target_attr (const char *args, location_t loc)
- static bool riscv_process_target_attr (tree args, location_t loc)
Thus, we can call `riscv_process_target_attr` with a `con
Some architectures may use ',' in the attribute string, but it is not
used as the separator for different targets. To avoid conflict, we
introduce a new macro TARGET_CLONES_ATTR_SEPARATOR to separate different
clones.
As an example, according to RISC-V C-API Specification [1], RISC-V allows
',' in
iscv-c-api-doc/pull/85
[3]
https://patchwork.sourceware.org/project/glibc/patch/tencent_71d182fbda6e8e57b80731dd218d8d5c7...@qq.com/
Yangyu Chen (11):
Introduce TARGET_CLONES_ATTR_SEPARATOR for RISC-V
RISC-V: Split riscv_process_target_attr with const char *args argument
RISC-V: Implement P
This patch implements the TARGET_OPTION_VALID_VERSION_ATTRIBUTE_P for
RISC-V. This hook is used to process attribute
((target_version ("..."))).
Co-Developed-by: Hank Chang
gcc/ChangeLog:
* config/riscv/riscv-protos.h
(riscv_option_valid_version_attribute_p): Declare.
(r
> On Oct 21, 2024, at 10:41, Kito Cheng wrote:
>
> Could you add testcases? Also, could you splitted that into smaller
> patches to make it easier to review?
>
Done!
Link: https://patchwork.sourceware.org/project/gcc/list/?series=39772
This patch adds test cases for the Function Multi-Versioning (FMV)
feature for RISC-V, which reuses the existing test cases from the
aarch64 and ported them to RISC-V.
gcc/testsuite/ChangeLog:
* g++.target/riscv/mv-symbols1.C: New test.
* g++.target/riscv/mv-symbols2.C: New test.
This patch implements the TARGET_GENERATE_VERSION_DISPATCHER_BODY and
TARGET_GET_FUNCTION_VERSIONS_DISPATCHER for RISC-V. This is used to
generate the dispatcher function and get the dispatcher function for
function multiversioning.
This patch copies many codes from commit 0cfde688e213 ("[aarch64]
To ensure that the target_version attribute is applied after target
attributes.
gcc/ChangeLog:
* config/riscv/riscv-target-attr.cc
(riscv_option_valid_attribute_p): Reapply target_version
attribute after target attribute
---
gcc/config/riscv/riscv-target-attr.cc | 13
When the callee is versioned but the caller is not, we should not inline
the callee into the caller, to prevent the default version of the callee
from being inlined into a not versioned caller.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_can_inline_p): Refuse to inline
when call
This patch implements the TARGET_MANGLE_DECL_ASSEMBLER_NAME for RISC-V.
This is used to add function multiversioning suffixes to the assembler
name.
gcc/ChangeLog:
* config/riscv/riscv.cc
(riscv_mangle_decl_assembler_name): New function.
(TARGET_MANGLE_DECL_ASSEMBLER_NAME)
This patch adds the priority syntax parser to support the Function
Multi-Versioning (FMV) feature in RISC-V. This feature allows users to
specify the priority of the function version in the attribute syntax.
Chnages based on RISC-V C-API PR:
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/85
This patch implements TARGET_COMPARE_VERSION_PRIORITY and
TARGET_OPTION_FUNCTION_VERSIONS for RISC-V.
The TARGET_COMPARE_VERSION_PRIORITY is implemented to compare the
priority of two function versions based on the rules defined in the
RISC-V C-API Doc PR #85:
https://github.com/riscv-non-isa/ris
This patch implements the riscv_minimal_hwprobe_feature_bits feature
for the RISC-V target. The feature bits are defined in the previous
patch [1] to provide bitmasks of ISA extensions that defined in RISC-V
C-API. Thus, we need a function to generate the feature bits for IFUNC
resolver to dispatch
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